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AlexandreSingerAlexandreSinger
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Merge pull request #3195 from verilog-to-routing/verilog_benchmark_fix_slang_errors
Resolve slang errors in VTR benchmarks
2 parents f4e3e3d + ab83993 commit e1f0d31

24 files changed

+7238
-1092
lines changed

‎vtr_flow/benchmarks/verilog/LU32PEEng.v‎

Lines changed: 44 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -508,7 +508,7 @@ begin
508508
end
509509
end
510510

511-
always @ (cur_state)
511+
always @ (*)
512512
begin
513513
case (cur_state)
514514
`MODE1:
@@ -1064,7 +1064,7 @@ begin
10641064
end
10651065

10661066
// connections to top block memory ports
1067-
always @ (topSourceSel or topWriteSel or curReadDataLU or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0)
1067+
always @ (*)
10681068
begin
10691069
if (topSourceSel == 1'b0)
10701070
case (topWriteSel)
@@ -1765,7 +1765,7 @@ else if (waitCycles >7'b0000000)
17651765
end
17661766

17671767
// determining next state of main FSM
1768-
always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1)
1768+
always @ (*)
17691769
begin
17701770
case (currentState)
17711771
`cSETUP:
@@ -1957,7 +1957,7 @@ begin
19571957
endcase
19581958
end
19591959

1960-
always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode)
1960+
always @ (*)
19611961
begin
19621962
if (currentRowState == `cDONE_FETCH_ROW)
19631963
doneFetchRow = 1;
@@ -1975,7 +1975,7 @@ begin
19751975
end
19761976

19771977
// second FSM that controls the control signals to temp_top block
1978-
always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState)
1978+
always @ (*)
19791979
begin
19801980
case (currentRowState)
19811981
`cFETCH_ROW:
@@ -2606,9 +2606,9 @@ assign j = |byteena_a;
26062606
assign q = subwire | dummy;
26072607
assign dummy = value_out & 1024'b0;
26082608

2609-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2610-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
2611-
dual_port_ram inst1(
2609+
dual_port_ram
2610+
# (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH))
2611+
inst1(
26122612
.clk (clk),
26132613
.we1(wren),
26142614
.we2(1'b0),
@@ -2650,9 +2650,9 @@ assign j = |byteena_a;
26502650
assign q = subwire | dummy;
26512651
assign dummy = value_out & 1024'b0;
26522652

2653-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2654-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
2655-
dual_port_ram inst1(
2653+
dual_port_ram
2654+
# (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH))
2655+
inst1(
26562656
.clk (clk),
26572657
.we1(wren),
26582658
.we2(1'b0),
@@ -2694,9 +2694,9 @@ assign j = |byteena_a;
26942694
assign q = subwire | dummy;
26952695
assign dummy = value_out & 1024'b0;
26962696

2697-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2698-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
2699-
dual_port_ram inst1(
2697+
dual_port_ram
2698+
# (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH))
2699+
inst1(
27002700
.clk (clk),
27012701
.we1(wren),
27022702
.we2(1'b0),
@@ -2737,9 +2737,9 @@ assign j = |byteena_a;
27372737
assign q = subwire | dummy;
27382738
assign dummy = value_out & 1024'b0;
27392739

2740-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2741-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
2742-
dual_port_ram inst1(
2740+
dual_port_ram
2741+
# (.ADDR_WIDTH(`rRAMSIZEWIDTH), .DATA_WIDTH(`RAMWIDTH))
2742+
inst1(
27432743
.clk (clk),
27442744
.we1(wren),
27452745
.we2(1'b0),
@@ -2779,9 +2779,9 @@ module top_ram (
27792779
assign q = sub_wire0 | dummy;
27802780
assign dummy = junk_output & 32'b0;
27812781

2782-
defparam inst2.ADDR_WIDTH = 12;
2783-
defparam inst2.DATA_WIDTH = 32;
2784-
dual_port_ram inst2(
2782+
dual_port_ram
2783+
# (.ADDR_WIDTH(12), .DATA_WIDTH(32))
2784+
inst2(
27852785
.clk (clk),
27862786
.we1(wren),
27872787
.we2(1'b0),
@@ -3324,9 +3324,10 @@ begin // : STATUS_COUNTER
33243324
else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
33253325
status_cnt <= status_cnt + 1'b1;
33263326
end
3327-
defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH;
3328-
defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH;
3329-
dual_port_ram ram_addr(
3327+
3328+
dual_port_ram
3329+
# (.ADDR_WIDTH(`rFIFORSIZEWIDTH), .DATA_WIDTH(`rFIFOINPUTWIDTH))
3330+
ram_addr(
33303331
.we1 (wrreq) , // write enable
33313332
.we2 (rdreq) , // Read enable
33323333
.addr1 (wr_pointer) , // address_0 input
@@ -3454,9 +3455,9 @@ begin // : STATUS_COUNTER
34543455
end
34553456
assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
34563457

3457-
defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH;
3458-
defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH;
3459-
dual_port_ram ram_addr(
3458+
dual_port_ram
3459+
# (.ADDR_WIDTH(`wFIFOSIZEWIDTH), .DATA_WIDTH(`wFIFOINPUTWIDTH))
3460+
ram_addr(
34603461
.we1 (wrreq) , // write enable
34613462
.we2 (rdreq) , // Read enable
34623463
.addr1 (wr_pointer) , // address_0 input
@@ -3531,9 +3532,9 @@ begin // : STATUS_COUNTER
35313532
status_cnt <= status_cnt + 1;
35323533
end
35333534

3534-
defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH;
3535-
defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH;
3536-
dual_port_ram ram_addr(
3535+
dual_port_ram
3536+
# (.ADDR_WIDTH(`aFIFOSIZEWIDTH), .DATA_WIDTH(`aFIFOWIDTH))
3537+
ram_addr(
35373538
.we1 (wrreq) , // write enable
35383539
.we2 (rdreq) , // Read enable
35393540
.addr1 (wr_pointer) , // address_0 input
@@ -3603,9 +3604,10 @@ begin // : STATUS_COUNTER
36033604
else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
36043605
status_cnt <= status_cnt + 1'b1;
36053606
end
3606-
defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH;
3607-
defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH;
3608-
dual_port_ram ram_addr(
3607+
3608+
dual_port_ram
3609+
# (.ADDR_WIDTH(`mFIFOSIZEWIDTH), .DATA_WIDTH(`mFIFOWIDTH))
3610+
ram_addr(
36093611
.we1 (wrreq) , // write enable
36103612
.we2 (rdreq) , // Read enable
36113613
.addr1 (wr_pointer) , // address_0 input
@@ -3676,7 +3678,7 @@ module fpu_add (clock, a1, b1, sum);
36763678
reg smaller; //smaller is 1 if a < b, 0 otherwise
36773679

36783680
//Shift mantissa's to have the same exponent
3679-
always @ (a or b) begin
3681+
always @ (*) begin
36803682
//a_exp = a[30:23];
36813683
//b_exp = b[30:23];
36823684
//a_man = {1'b1, a[22:0]};
@@ -3861,7 +3863,7 @@ module fpu_add (clock, a1, b1, sum);
38613863
end
38623864

38633865
//Perform the addition operation
3864-
always @ (a_man or b_man or a or b) begin
3866+
always @ (*) begin
38653867
if (a_man < b_man) begin
38663868
smaller = 1'b1;
38673869
end else begin
@@ -3906,7 +3908,7 @@ module fpu_add (clock, a1, b1, sum);
39063908
//Store the number
39073909
// we already have the sign.
39083910

3909-
always @ (sum_man or a_exp) begin
3911+
always @ (*) begin
39103912
if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent.
39113913
sum[22:0] = sum_man[23:1];
39123914
sum[30:23] = a_exp + 8'b00000001;
@@ -4044,7 +4046,7 @@ module fpu_div(clock, n, d, div);
40444046
end
40454047

40464048
//Find the exponent, store in div_exp.
4047-
always @ (n_exp or d_exp) begin
4049+
always @ (*) begin
40484050
if (n_exp >= d_exp) begin
40494051
div_exp = 8'b01111111 + (n_exp - d_exp);
40504052
end else begin
@@ -4057,12 +4059,12 @@ module fpu_div(clock, n, d, div);
40574059

40584060
//Store the result. Shift exponents appropriately. Store sign.
40594061
//Sign
4060-
always @ (n_sign or d_sign) begin
4062+
always @ (*) begin
40614063
div[31] = n_sign ^ d_sign;
40624064
end
40634065

40644066
//Mantissa and Exponent
4065-
always @ (div_man or div_exp) begin
4067+
always @ (*) begin
40664068
if (div_man[23]) begin //do nothing
40674069
div[22:0] = div_man[22:0];
40684070
div[30:23] = div_exp;
@@ -4209,7 +4211,7 @@ module div_24b(numer, denom, res);
42094211
// end
42104212

42114213
//res[23]
4212-
always @ (denom_pad or numer23) begin
4214+
always @ (*) begin
42134215

42144216
if (denom_pad[23:0] <= numer23[46:23]) begin
42154217
res[23] = 1'b1;
@@ -4854,7 +4856,7 @@ assign shiftb = b[23 - 1] ? 1 :
48544856
// If number is denorm, shift the significand the appropriate amount
48554857
// assign shifteda = a[`WSIG-1:0] << shifta;
48564858
//Must have constant shifts for ODIN
4857-
always @ (shifta or a) begin
4859+
always @ (*) begin
48584860
case (shifta)
48594861
5'b00001: begin
48604862
shifteda = a[`WSIG-1:0] << 5'b00001;
@@ -4957,7 +4959,7 @@ assign shiftb = b[23 - 1] ? 1 :
49574959
assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]};
49584960

49594961
// assign shiftedb = b[`WSIG-1:0] << shiftb;
4960-
always @ (shiftb or b) begin
4962+
always @ (*) begin
49614963
case (shiftb)
49624964
5'b00001: begin
49634965
shiftedb = b[`WSIG-1:0] << 5'b00001;
@@ -5170,7 +5172,7 @@ module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss);
51705172
// shift significand
51715173
//assign postshift = preshift >> actualshiftamt;
51725174
//We can only have constant shifts for ODIN:
5173-
always @ (actualshiftamt or preshift) begin
5175+
always @ (*) begin
51745176
case (actualshiftamt)
51755177
5'b00001: begin
51765178
postshift = preshift >> 5'b00001;

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