aarch64: verify popcnt rules (bytecodealliance#217)

Verify `popcnt` rules.

Requires a slight rewrite of the `mov_to_fpu` rules to avoid recursion,
and therefore allow chaining.

Extracted from original implementation in bytecodealliance#189.

Updates avanhatt#34

Co-authored-by: Vaishu Chintam <[email protected]>
Co-authored-by: Alexa VanHattum <[email protected]>

Author: 3 people

cranelift/codegen/src/inst_specs.isle

@@ -235,6 +235,10 @@
     (provide (= result (clz (rev x)))))
 (instantiate ctz bv_unary_8_to_64)
 
+(spec (popcnt x)
+    (provide (= result (popcnt x))))
+(instantiate popcnt bv_unary_8_to_64)
+
 (spec (load flags p offset)
     (modifies clif_load loaded_value)
     (provide

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -2869,13 +2869,16 @@
 
 ;; Helper for emitting `MInst.MovToFpu` instructions.
 (decl mov_to_fpu (Reg ScalarSize) Reg)
+(attr mov_to_fpu (veri chain))
 (rule (mov_to_fpu x size)
       (let ((dst WritableReg (temp_writable_reg $I8X16))
             (_ Unit (emit (MInst.MovToFpu dst x size))))
         dst))
 (rule 1 (mov_to_fpu x (ScalarSize.Size16))
         (if-let $false (use_fp16))
-        (mov_to_fpu x (ScalarSize.Size32)))
+        (let ((dst WritableReg (temp_writable_reg $I8X16))
+             (_ Unit (emit (MInst.MovToFpu dst x (ScalarSize.Size32)))))
+         dst))
 
 ;; Helper for emitting `MInst.FpuMoveFPImm` instructions.
 (decl fpu_move_fp_imm (ASIMDFPModImm ScalarSize) Reg)

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -1899,25 +1899,25 @@
 ;;     if ty == i128:
 ;;         mov out_hi, 0
 
-(rule (lower (has_type $I8 (popcnt x)))
+(rule popcnt_8 (lower (has_type $I8 (popcnt x)))
       (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
             (nbits Reg (vec_cnt tmp (VectorSize.Size8x8))))
         (mov_from_vec nbits 0 (ScalarSize.Size8))))
 
 ;; Note that this uses `addp` instead of `addv` as it's usually cheaper.
-(rule (lower (has_type $I16 (popcnt x)))
+(rule popcnt_16 (lower (has_type $I16 (popcnt x)))
       (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
             (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
             (added Reg (addp nbits nbits (VectorSize.Size8x8))))
         (mov_from_vec added 0 (ScalarSize.Size8))))
 
-(rule (lower (has_type $I32 (popcnt x)))
+(rule popcnt_32 (lower (has_type $I32 (popcnt x)))
       (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
             (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
             (added Reg (addv nbits (VectorSize.Size8x8))))
         (mov_from_vec added 0 (ScalarSize.Size8))))
 
-(rule (lower (has_type $I64 (popcnt x)))
+(rule popcnt_64 (lower (has_type $I64 (popcnt x)))
       (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size64)))
             (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
             (added Reg (addv nbits (VectorSize.Size8x8))))

cranelift/codegen/src/prelude.isle

@@ -409,6 +409,7 @@
 
 (extern const $I8X8 Type)
 (extern const $I8X16 Type)
+(model I8X16 (const 128))
 (extern const $I16X4 Type)
 (extern const $I16X8 Type)
 (extern const $I32X2 Type)