@@ -165,11 +165,6 @@ struct __attribute__((__packed__)) dma_xilinx_axi_dma_sg_descriptor {
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uint32_t app4 ;
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} __aligned (64 );
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- __aligned (64 ) static struct dma_xilinx_axi_dma_sg_descriptor
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- descriptors_tx [CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX ] = {0 };
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- __aligned (64 ) static struct dma_xilinx_axi_dma_sg_descriptor
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- descriptors_rx [CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX ] = {0 };
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-
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enum AxiDmaDirectionRegister {
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/* DMA control register */
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/* bitfield, masks defined above */
@@ -234,6 +229,11 @@ struct dma_xilinx_axi_dma_channel {
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struct dma_xilinx_axi_dma_data {
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struct dma_context ctx ;
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struct dma_xilinx_axi_dma_channel * channels ;
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+
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+ __aligned (64 ) struct dma_xilinx_axi_dma_sg_descriptor
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+ descriptors_tx [CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX ];
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+ __aligned (64 ) struct dma_xilinx_axi_dma_sg_descriptor
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+ descriptors_rx [CONFIG_DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX ];
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};
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static inline int dma_xilinx_axi_dma_lock_irq (const struct device * dev , const uint32_t channel_num )
@@ -916,14 +916,16 @@ static int dma_xilinx_axi_dma_init(const struct device *dev)
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return - EINVAL ;
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}
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- data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].descriptors = descriptors_tx ;
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- data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].num_descriptors = ARRAY_SIZE (descriptors_tx );
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+ data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].descriptors = data -> descriptors_tx ;
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+ data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].num_descriptors =
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+ ARRAY_SIZE (data -> descriptors_tx );
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data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].channel_regs =
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cfg -> reg + XILINX_AXI_DMA_MM2S_REG_OFFSET ;
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data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].direction = MEMORY_TO_PERIPHERAL ;
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- data -> channels [XILINX_AXI_DMA_RX_CHANNEL_NUM ].descriptors = descriptors_rx ;
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- data -> channels [XILINX_AXI_DMA_RX_CHANNEL_NUM ].num_descriptors = ARRAY_SIZE (descriptors_rx );
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+ data -> channels [XILINX_AXI_DMA_RX_CHANNEL_NUM ].descriptors = data -> descriptors_rx ;
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+ data -> channels [XILINX_AXI_DMA_RX_CHANNEL_NUM ].num_descriptors =
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+ ARRAY_SIZE (data -> descriptors_rx );
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data -> channels [XILINX_AXI_DMA_RX_CHANNEL_NUM ].channel_regs =
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cfg -> reg + XILINX_AXI_DMA_S2MM_REG_OFFSET ;
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data -> channels [XILINX_AXI_DMA_TX_CHANNEL_NUM ].direction = PERIPHERAL_TO_MEMORY ;
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