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andrewrkandrewrk
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Merge pull request #6255 from joachimschmidt557/stage2-arm
stage2 ARM: more instructions, return values, parameters
2 parents 6aa668e + fb58fb2 commit da596b7

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4 files changed

+642
-140
lines changed

4 files changed

+642
-140
lines changed

‎src/codegen.zig

Lines changed: 154 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -570,6 +570,39 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
570570
try self.dbgSetEpilogueBegin();
571571
}
572572
},
573+
.arm => {
574+
const cc = self.fn_type.fnCallingConvention();
575+
if (cc != .Naked) {
576+
// push {fp, lr}
577+
// mov fp, sp
578+
// sub sp, sp, #reloc
579+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.push(.al, .{ .fp, .lr }).toU32());
580+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .fp, Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none)).toU32());
581+
// TODO: prepare stack for local variables
582+
// const backpatch_reloc = try self.code.addManyAsArray(4);
583+
584+
try self.dbgSetPrologueEnd();
585+
586+
try self.genBody(self.mod_fn.analysis.success);
587+
588+
// Backpatch stack offset
589+
// const stack_end = self.max_end_stack;
590+
// const aligned_stack_end = mem.alignForward(stack_end, self.stack_align);
591+
// mem.writeIntLittle(u32, backpatch_reloc, Instruction.sub(.al, .sp, .sp, Instruction.Operand.imm()));
592+
593+
try self.dbgSetEpilogueBegin();
594+
595+
// mov sp, fp
596+
// pop {fp, pc}
597+
// TODO: return by jumping to this code, use relocations
598+
// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
599+
// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
600+
} else {
601+
try self.dbgSetPrologueEnd();
602+
try self.genBody(self.mod_fn.analysis.success);
603+
try self.dbgSetEpilogueBegin();
604+
}
605+
},
573606
else => {
574607
try self.dbgSetPrologueEnd();
575608
try self.genBody(self.mod_fn.analysis.success);
@@ -1461,7 +1494,35 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
14611494
}
14621495
},
14631496
.arm => {
1464-
if (info.args.len > 0) return self.fail(inst.base.src, "TODO implement fn args for {}", .{self.target.cpu.arch});
1497+
for (info.args) |mc_arg, arg_i| {
1498+
const arg = inst.args[arg_i];
1499+
const arg_mcv = try self.resolveInst(inst.args[arg_i]);
1500+
1501+
switch (mc_arg) {
1502+
.none => continue,
1503+
.undef => unreachable,
1504+
.immediate => unreachable,
1505+
.unreach => unreachable,
1506+
.dead => unreachable,
1507+
.embedded_in_code => unreachable,
1508+
.memory => unreachable,
1509+
.compare_flags_signed => unreachable,
1510+
.compare_flags_unsigned => unreachable,
1511+
.register => |reg| {
1512+
try self.genSetReg(arg.src, reg, arg_mcv);
1513+
// TODO interact with the register allocator to mark the instruction as moved.
1514+
},
1515+
.stack_offset => {
1516+
return self.fail(inst.base.src, "TODO implement calling with parameters in memory", .{});
1517+
},
1518+
.ptr_stack_offset => {
1519+
return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_stack_offset arg", .{});
1520+
},
1521+
.ptr_embedded_in_code => {
1522+
return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_embedded_in_code arg", .{});
1523+
},
1524+
}
1525+
}
14651526

14661527
if (inst.func.cast(ir.Inst.Constant)) |func_inst| {
14671528
if (func_inst.val.cast(Value.Payload.Function)) |func_val| {
@@ -1476,13 +1537,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
14761537
else
14771538
unreachable;
14781539

1479-
// TODO only works with leaf functions
1480-
// at the moment, which works fine for
1481-
// Hello World, but not for real code
1482-
// of course. Add pushing lr to stack
1483-
// and popping after call
14841540
try self.genSetReg(inst.base.src, .lr, .{ .memory = got_addr });
1485-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
1541+
1542+
// TODO: add Instruction.supportedOn
1543+
// function for ARM
1544+
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
1545+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
1546+
} else {
1547+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
1548+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
1549+
}
14861550
} else {
14871551
return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
14881552
}
@@ -1602,7 +1666,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
16021666
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
16031667
},
16041668
.arm => {
1605-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
1669+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
1670+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
1671+
// TODO: jump to the end with relocation
1672+
// // Just add space for an instruction, patch this later
1673+
// try self.code.resize(self.code.items.len + 4);
1674+
// try self.exitlude_jump_relocs.append(self.gpa, self.code.items.len - 4);
16061675
},
16071676
else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}),
16081677
}
@@ -2214,14 +2283,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
22142283
// least amount of necessary instructions (use
22152284
// more intelligent rotating)
22162285
if (x <= math.maxInt(u8)) {
2217-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2286+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
22182287
return;
22192288
} else if (x <= math.maxInt(u16)) {
22202289
// TODO Use movw Note: Not supported on
22212290
// all ARM targets!
22222291

2223-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2224-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2292+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2293+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
22252294
} else if (x <= math.maxInt(u32)) {
22262295
// TODO Use movw and movt Note: Not
22272296
// supported on all ARM targets! Also TODO
@@ -2233,20 +2302,28 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
22332302
// orr reg, reg, #0xbb, 24
22342303
// orr reg, reg, #0xcc, 16
22352304
// orr reg, reg, #0xdd, 8
2236-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2237-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2238-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
2239-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
2305+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2306+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2307+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
2308+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
22402309
return;
22412310
} else {
22422311
return self.fail(src, "ARM registers are 32-bit wide", .{});
22432312
}
22442313
},
2314+
.register => |src_reg| {
2315+
// If the registers are the same, nothing to do.
2316+
if (src_reg.id() == reg.id())
2317+
return;
2318+
2319+
// mov reg, src_reg
2320+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none)).toU32());
2321+
},
22452322
.memory => |addr| {
22462323
// The value is in memory at a hard-coded address.
22472324
// If the type is a pointer, it means the pointer address is at this memory location.
22482325
try self.genSetReg(src, reg, .{ .immediate = addr });
2249-
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, Instruction.Offset.none).toU32());
2326+
mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, .{ .offset = Instruction.Offset.none }).toU32());
22502327
},
22512328
else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
22522329
},
@@ -2702,6 +2779,55 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
27022779
else => return self.fail(src, "TODO implement function parameters for {} on x86_64", .{cc}),
27032780
}
27042781
},
2782+
.arm => {
2783+
switch (cc) {
2784+
.Naked => {
2785+
assert(result.args.len == 0);
2786+
result.return_value = .{ .unreach = {} };
2787+
result.stack_byte_count = 0;
2788+
result.stack_align = 1;
2789+
return result;
2790+
},
2791+
.Unspecified, .C => {
2792+
// ARM Procedure Call Standard, Chapter 6.5
2793+
var ncrn: usize = 0; // Next Core Register Number
2794+
var nsaa: u32 = 0; // Next stacked argument address
2795+
2796+
for (param_types) |ty, i| {
2797+
if (ty.abiAlignment(self.target.*) == 8) {
2798+
// Round up NCRN to the next even number
2799+
ncrn += ncrn % 2;
2800+
}
2801+
2802+
const param_size = @intCast(u32, ty.abiSize(self.target.*));
2803+
if (std.math.divCeil(u32, param_size, 4) catch unreachable <= 4 - ncrn) {
2804+
if (param_size <= 4) {
2805+
result.args[i] = .{ .register = c_abi_int_param_regs[ncrn] };
2806+
ncrn += 1;
2807+
} else {
2808+
return self.fail(src, "TODO MCValues with multiple registers", .{});
2809+
}
2810+
} else if (ncrn < 4 and nsaa == 0) {
2811+
return self.fail(src, "TODO MCValues split between registers and stack", .{});
2812+
} else {
2813+
ncrn = 4;
2814+
if (ty.abiAlignment(self.target.*) == 8) {
2815+
if (nsaa % 8 != 0) {
2816+
nsaa += 8 - (nsaa % 8);
2817+
}
2818+
}
2819+
2820+
result.args[i] = .{ .stack_offset = nsaa };
2821+
nsaa += param_size;
2822+
}
2823+
}
2824+
2825+
result.stack_byte_count = nsaa;
2826+
result.stack_align = 4;
2827+
},
2828+
else => return self.fail(src, "TODO implement function parameters for {} on arm", .{cc}),
2829+
}
2830+
},
27052831
else => if (param_types.len != 0)
27062832
return self.fail(src, "TODO implement codegen parameters for {}", .{self.target.cpu.arch}),
27072833
}
@@ -2720,6 +2846,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
27202846
},
27212847
else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
27222848
},
2849+
.arm => switch (cc) {
2850+
.Naked => unreachable,
2851+
.Unspecified, .C => {
2852+
const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
2853+
if (ret_ty_size <= 4) {
2854+
result.return_value = .{ .register = c_abi_int_return_regs[0] };
2855+
} else {
2856+
return self.fail(src, "TODO support more return types for ARM backend", .{});
2857+
}
2858+
},
2859+
else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
2860+
},
27232861
else => return self.fail(src, "TODO implement codegen return values for {}", .{self.target.cpu.arch}),
27242862
}
27252863
return result;

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