__NVIC_EnableIRQ compiler barriers #510
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Add a macro to represent a compiler optimisation barrier - memory loads and stores can not be reordered across this barrier.
__NVIC_DisableIRQ and __NVIC_EnableIRQ can be used to function as a
mutex-style protection lock against a particular interrupt handler,
similar to __disable_irq and __enable_irq for all interrupts.
However, __NVIC_EnableIRQ, unlike a mutex unlock or __enable_irq, had no
compiler barriers. Being just a volatile write, in the following code
sequence:
NVIC_DisableIRQ(devx);
// modify some RAM accessed by devx IRQ handler
NVIC_EnableIRQ(devx);
there would be nothing preventing the RAM accesses from moved below the
NVIC_EnableIRQ.
Add barriers to NVIC_EnableIRQ, so that the above code works the same as
a mutex or __disable_irq, without any added need to mark the shared RAM
as volatile.
Fixes issue ARM-software#493
ghost
reviewed
Jan 17, 2019
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__NVIC_DisableIRQ and __NVIC_EnableIRQ can be used to function as a mutex-style protection lock against a particular interrupt handler, similar to __disable_irq and __enable_irq for all interrupts.
However, __NVIC_EnableIRQ, unlike a mutex unlock or __enable_irq, had no compiler barriers. Being just a volatile write, in the following code sequence:
there would be nothing preventing the RAM accesses from moved below the NVIC_EnableIRQ.
Add barriers to NVIC_EnableIRQ, so that the above code works the same as a mutex or __disable_irq, without any added need to mark the shared RAM as volatile.
Fixes issue #493