Add target GR-PEACH #132
Add target GR-PEACH #132
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It branches in processing for Cortex-A by macro TARGET_MCU_CORTEX_A. A "swd_host.c" for Cortex-A is created as "swd_host_ca.c". The binary inspection was made comparison in 3 bytes of head of the data because there was no NVIC in Cortex-A. Comparative data can be set for each board by macro BINARY_DETECTION.
Our Flash will take more than 20 seconds to chip erase. Therefore, we have added the process of writing a program with partial erase. Selective erase becomes effective by macro FLASH_PARTIAL_ERASE.
A flash of rza1h is outside the chip, and the flash and port may be different from every board. So it was made the following path. "/source/target/renesas/rza1h/gr-peach/"
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Hi @d-kato thanks for the PR. Would it be possible to move the partial erase into a second PR to make testing and merging easier? |
| #ifdef FLASH_PARTIAL_ERASE | ||
| // Processing for low-speed devices of chip erasure. | ||
| flash_manager_printf(" skip intf->erase_chip\r\n"); | ||
| #else |
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FLASH_PARTIAL_ERASE is a very useful feature. This would be nice as a run-time configurable value. Maybe a function to set the mode?
flash_manager_init(const flash_intf_t *flash_intf, flash_mode_t)
or maybe a seperate function
flash_manager_mode(CHIP_ERASE) / flash_manager_mode(SECTOR_ERASE)
What do you think @d-kato?
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I think the "flash_manager_init()" is preferred.
In the case of "flash_manager_mode()", it might appear to be able to change at any time.
Fixed the following. https://github.com/mbedmicro/DAPLink/pull/132/files/b6a53f244ca2fb9e9d523945db955b2511fa0e1b#r74541708 https://github.com/mbedmicro/DAPLink/pull/132/files/b6a53f244ca2fb9e9d523945db955b2511fa0e1b#r74541791 https://github.com/mbedmicro/DAPLink/pull/132/files/b6a53f244ca2fb9e9d523945db955b2511fa0e1b#r74542380
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Hi @c1728p9 , |
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Hi @d-kato unfortunately, I haven't had time to test this so it won't make it into 0242. I'll try to get to this by the next release. I very much want Cortex A / Peach support in DAPLink so thanks for the PR. |
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I close this PR for rebase. |
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It branches in processing for Cortex-A by macro TARGET_MCU_CORTEX_A.
A "swd_host.c" for Cortex-A is created as "swd_host_ca.c".
The binary inspection was made comparison in 3 bytes of head of the data because there was no NVIC in Cortex-A.
Comparative data can be set for each board by macro BINARY_DETECTION.
Our Flash will take more than 20 seconds to chip erase.
Therefore, we have added the process of writing a program with partial erase.
Selective erase becomes effective by macro FLASH_PARTIAL_ERASE.
A flash of rza1h is outside the chip, and the flash and port may be different from every board.
So it was made the following path.
"/source/target/renesas/rza1h/gr-peach/"