Edit on Toolchain linker files for stm32L071xx target

targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld

@@ -29,7 +29,7 @@
 #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
     /* This value is normally defined by the tools
        to 0x1000 for bare metal and 0x400 for RTOS */
-    #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400
 #endif
 
 /* Round up VECTORS_SIZE to 8 bytes */

targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S

@@ -1,29 +1,42 @@
-/* mbed Microcontroller Library
- * SPDX-License-Identifier: BSD-3-Clause
- ******************************************************************************
- *
- * Copyright (c) 2020 STMicroelectronics. 
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the 
- * License. You may obtain a copy of the License at:
- *                        opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- * @file      startup_stm32l071xx.s
- * @author    MCD Application Team
- * @brief     STM32L071xx Devices vector table for GCC toolchain.
- *            This module performs:
- *                - Set the initial SP
- *                - Set the initial PC == Reset_Handler,
- *                - Set the vector table entries with the exceptions ISR address
- *                - Branches to main in the C library (which eventually
- *                  calls main()).
- *            After Reset the Cortex-M0+ processor is in Thread mode,
- *            priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- */
+/**
+  ******************************************************************************
+  * @file      startup_stm32l071xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L071xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0+ processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * 
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
 
   .syntax unified
   .cpu cortex-m0plus
@@ -48,9 +61,9 @@ defined in linker script */
     .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -85,12 +98,13 @@ LoopFillZerobss:
 /* Call the clock system intitialization function.*/
   bl  SystemInit
 /* Call static constructors */
-    bl __libc_init_array
+  //bl __libc_init_array
 /* Call the application's entry point.*/
-  bl  main
+  //bl  main
+  bl _start
 
 LoopForever:
-    b LoopForever
+  b LoopForever
 
 
 .size  Reset_Handler, .-Reset_Handler

targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h

@@ -32,7 +32,7 @@
 #define MBED_RAM_SIZE  0x5000  // 20 KB
 #endif
 
-#define NVIC_NUM_VECTORS        32
+#define NVIC_NUM_VECTORS        48
 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
 
 #endif