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[TARGET_STM32F3]: Update Hal 1.5.0 #1977

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Merged
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Jul 1, 2016
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[TARGET_STM32F3]: Update Hal 1.5.0 #1977

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16,120 changes: 11,212 additions & 4,908 deletions hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/stm32f303xc.h
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73 changes: 48 additions & 25 deletions hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/stm32f3xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.0.1
* @date 18-June-2014
* @version V2.3.0
* @date 29-April-2015
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
Expand All @@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -64,31 +64,48 @@
* @{
*/

/**
* @brief STM32 Family
*/
#if !defined (STM32F3)
#define STM32F3
#endif /* STM32F3 */

/* Uncomment the line below according to the target STM32 device used in your
application
*/

#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
!defined (STM32F302x8) && !defined (STM32F302xC) && \
!defined (STM32F303x8) && \
!defined (STM32F303xC) && !defined (STM32F358xx) && \
!defined (STM32F373xC) && !defined (STM32F378xx) && \
!defined (STM32F334x8) && !defined (STM32F328xx)
#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
!defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
!defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
!defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
!defined (STM32F373xC) && !defined (STM32F378xx)

/* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
STM32F301R6 and STM32F301R8 Devices */
/* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
STM32F302R6 and STM32F302R8 Devices */
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
STM32F302VB and STM32F302VC Devices */
/* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
STM32F302VD and STM32F302ZD Devices */
/* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
STM32F303R6 and STM32F303R8 Devices */
#define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC,
#define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
STM32F303VB and STM32F303VC Devices */
/* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
STM32F303VD and STM32F303ZD Devices */
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
STM32F373R8, STM32F373RB, STM32F373RC,
STM32F373V8, STM32F373VB and STM32F373VC Devices */
/* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
/* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8,
STM32F334C4, STM32F334C6, STM32F334C8,
STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
/* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
/* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
/* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
/* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
/* #define STM32F398xx */ /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
#endif

/* Tip: To avoid modifying this file each time you need to switch between these
Expand All @@ -100,21 +117,21 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V2.0.1
*/
#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F3_CMSIS_VERSION_RC))

/**
* @}
*/
Expand All @@ -129,10 +146,14 @@
#include "stm32f302x8.h"
#elif defined(STM32F302xC)
#include "stm32f302xc.h"
#elif defined(STM32F302xE)
#include "stm32f302xe.h"
#elif defined(STM32F303x8)
#include "stm32f303x8.h"
#elif defined(STM32F303xC)
#include "stm32f303xc.h"
#elif defined(STM32F303xE)
#include "stm32f303xe.h"
#elif defined(STM32F373xC)
#include "stm32f373xc.h"
#elif defined(STM32F334x8)
Expand All @@ -145,6 +166,8 @@
#include "stm32f358xx.h"
#elif defined(STM32F378xx)
#include "stm32f378xx.h"
#elif defined(STM32F398xx)
#include "stm32f398xx.h"
#else
#error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
#endif
Expand Down
23 changes: 12 additions & 11 deletions hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.c
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Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.1.0
* @date 12-Sept-2014
* @version V2.3.0
* @date 29-April-2015
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
Expand Down Expand Up @@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -147,6 +147,7 @@
*/
uint32_t SystemCoreClock = 72000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};

/**
* @}
Expand Down Expand Up @@ -185,28 +186,28 @@ void SystemInit(void)

/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
RCC->CR |= 0x00000001U;

/* Reset CFGR register */
RCC->CFGR &= 0xF87FC00C;
RCC->CFGR &= 0xF87FC00CU;

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->CR &= 0xFEF6FFFFU;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= 0xFFFBFFFFU;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
RCC->CFGR &= 0xFF80FFFFU;

/* Reset PREDIV1[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
RCC->CFGR2 &= 0xFFFFFFF0U;

/* Reset USARTSW[1:0], I2CSW and TIMs bits */
RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
RCC->CFGR3 &= 0xFF00FCCCU;

/* Disable all interrupts */
RCC->CIR = 0x00000000;
RCC->CIR = 0x00000000U;

#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Expand Down
8 changes: 5 additions & 3 deletions hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.h
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Expand Up @@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.1.0
* @date 12-Sept-2014
* @version V2.3.0
* @date 29-April-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -74,6 +74,8 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */


/**
Expand Down
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