Skip to content
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

This file was deleted.

7,508 changes: 0 additions & 7,508 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h

This file was deleted.

This file was deleted.

This file was deleted.

63 changes: 0 additions & 63 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h

This file was deleted.

Original file line number Diff line number Diff line change
@@ -132,7 +132,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;

/* Used to gain time after DeepSleep in case HSI is used */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
@@ -163,6 +162,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
return 0; // FAIL
}

/* Select HSI48 as USB clock source */
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}

/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -173,12 +180,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
return 0; // FAIL
}

RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}

/* Output clock on MCO1 pin(PA8) for debugging purpose */
//if (bypass == 0)
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
Original file line number Diff line number Diff line change
@@ -128,7 +128,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1
DCD LCD_IRQHandler ; LCD
DCD USB_IRQHandler ; USB

__Vectors_End

__Vectors_Size EQU __Vectors_End - __Vectors
@@ -139,7 +139,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
@@ -213,7 +213,7 @@ TSC_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_6_7_IRQHandler
ADC1_COMP_IRQHandler
ADC1_COMP_IRQHandler
LPTIM1_IRQHandler
TIM2_IRQHandler
TIM6_DAC_IRQHandler
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
; 64KB FLASH (0x10000) + 8KB RAM (0x2000)
LR_IROM1 0x08000000 0x10000 { ; load region size_region

ER_IROM1 0x08000000 0x10000 { ; load address = execution address
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
; 64KB FLASH (0x10000) + 8KB RAM (0x2000)
LR_IROM1 0x08000000 0x10000 { ; load region size_region

ER_IROM1 0x08000000 0x10000 { ; load address = execution address
4 changes: 2 additions & 2 deletions targets/targets.json
Original file line number Diff line number Diff line change
@@ -1279,7 +1279,7 @@
"inherits": ["FAMILY_STM32"],
"supported_form_factors": ["ARDUINO", "MORPHO"],
"core": "Cortex-M0+",
"extra_labels_add": ["STM32L0", "STM32L053R8"],
"extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1493,7 +1493,7 @@
"DISCO_L053C8": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M0+",
"extra_labels_add": ["STM32L0", "STM32L053C8"],
"extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
"macros": ["RTC_LSI=1"],
"config": {
"clock_source": {