New support for the STM NUCLEO_L433RC-P board #5230

helmut64 · 2017-10-01T18:05:57Z

Dear ST and MBED team,
I added support for a new the target NUCLEO_L433RC.
The L433 is pretty much like the L432, but STDIO pins and peripherals are different.
I tested this using the official NUCLEO_L433RC board from STM.
I have not done the job for export_test.py and tests.py as documented in “steps-to-create-a-new-STM32-platform” because the documentation does not match file files.
Regards Helmut

bcostm · 2017-10-02T07:31:37Z

Thanks a lot ! We'll review the code and run mbed2 and mbed5 tests for all toolchains.

bcostm · 2017-10-02T07:43:24Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PinNames.h

+  PB_14 = 0x1E,
+  PB_15 = 0x1F,
+
+#ifndef STM32L433_48PINS // 48 pin versions don't have PC0-PC15 pins


Where is this define set ?

The define STM32L433_48PINS can be set by users to limited to pins to the 48 pin versions of the STM433 MCUs, by default this is included because the Nucleo board uses the 64 pin version.
The define STM32L433_100PINS can be set by users to extend the pins to the 100 pin versions of the STM433 MCUs.

The is reasonable to be more flexible for the pin definition which allows many more 433 MCUs to be used.

The __weak of PinMaps in the PeripheralPins.c allows to extend this for other MCUs, another option would be to use the PeripheralPins.c for the 100 pin MCU version which is a superset of the 64 pin version.

OK. The __weak is a good idea and we prefer this solution.

bcostm · 2017-10-02T09:09:43Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+
+//*** PWM ***
+// TODO: Timers/PWM for the L433xx need to be reviewed/completed,
+//       Check for TIM6/TIM7 of the 433


I don't see any PWM pins on TIM6/TIM7 in the DataSheet.

Can you add the "_ALTx" on the pins that we don't use ? You will need also to add the _ALTx definitions in the PinNames.h file (see NUCLEO_F429ZI for example).

bcostm · 2017-10-02T09:12:51Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+//*** SERIAL ***
+
+__weak const PinMap PinMap_UART_TX[] = {
+//     {PA_2,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},


Can you add a comment:
// Cannot be used as UART2 is used for STDIO

bcostm · 2017-10-02T09:13:02Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+};
+
+__weak const PinMap PinMap_UART_RX[] = {
+//    {PA_3,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},


Can you add a comment:
// Cannot be used as UART2 is used for STDIO

bcostm · 2017-10-02T09:14:05Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+    {PA_1,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_1,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:14:20Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+
+__weak const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:14:31Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+    {PA_6,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_13,      LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:14:42Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+    {PA_7,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:14:56Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+__weak const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_4,       SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:15:10Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+__weak const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:15:18Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+__weak const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},


Can you add the "_ALTx" on the pins that we don't use ?

bcostm · 2017-10-02T09:22:39Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+ * I declared all mapping tables as weak to allow custom overwrites for similar MCU models
+ * The busy GPIOs e.g. PA_3/3 are still declared to allow reusing them for other IO.
+ */
+


Can you please replace the 2 above notes with this one:

//============================================================================== // Notes // // - The pins mentionned Px_y_ALTz are alternative possibilities which use other // HW peripheral instances. You can use them the same way as any other "normal" // pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board // pinout image on mbed.org. // // - The pins which are connected to other components present on the board have // the comment "Connected to xxx". The pin function may not work properly in this // case. These pins may not be displayed on the board pinout image on mbed.org. // Please read the board reference manual and schematic for more information. // // - All mapping tables are declared as weak to allow custom overwrites for similar MCU models. // //==============================================================================

bcostm · 2017-10-02T09:37:42Z

targets/targets.json

+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0770"],


I have the ID 0779 when I connect my NUCLEO-L433RC-P.

Can you confirm the ID you see in the MBED.HTM file (first 4 digits in the code field) ?

<meta http-equiv="refresh" content="0; url=http://mbed.org/device/?code=07790221172C637A2868F53E"/>

Yes my Code is: code=07790221172F6363286BF527

bcostm · 2017-10-02T10:56:12Z

As the board is a NUCLEO_L433RC-P can you please change the name is this PR title and also in the files ?

bcostm · 2017-10-02T10:58:09Z

targets/targets.json

@@ -1345,6 +1345,23 @@
        "release_versions": ["2", "5"],
        "device_name": "STM32L432KC"
    },
+    "NUCLEO_L433RC": {


Please change the name to NUCLEO_L433RC_P

bcostm · 2017-10-02T10:59:01Z

tools/build_travis.py

@@ -54,6 +54,7 @@
    { "target": "NUCLEO_F411RE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
    { "target": "NUCLEO_F412ZG",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
    { "target": "NUCLEO_L432KC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L433RC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },


NUCLEO_L433RC_P

bcostm · 2017-10-02T10:59:39Z

tools/export/sw4stm32/__init__.py

@@ -244,6 +244,11 @@ class Sw4STM32(GNUARMEclipse):
            'name': 'NUCLEO-L432KC',
            'mcuId': 'STM32L432KCUx'
        },
+        'NUCLEO_L433RC':


NUCLEO_L433RC_P

bcostm · 2017-10-02T11:05:44Z

tools/export/sw4stm32/__init__.py

@@ -244,6 +244,11 @@ class Sw4STM32(GNUARMEclipse):
            'name': 'NUCLEO-L432KC',
            'mcuId': 'STM32L432KCUx'
        },
+        'NUCLEO_L433RC':
+        {
+            'name': 'NUCLEO-L433RC',


NUCLEO-L433RC-P

bcostm · 2017-10-02T11:06:00Z

tools/export/sw4stm32/__init__.py

+        'NUCLEO_L433RC':
+        {
+            'name': 'NUCLEO-L433RC',
+            'mcuId': 'STM32L433RCUx'


STM32L433RCTxP

helmut64 · 2017-10-02T12:56:58Z

@bcostm I did all the changes you proposed, however no ALTx changes.
I don't get the ALTx concept, maybe you can explain it to me.
Thank you for reviewing the changes and getting this done together.

ohagendorf · 2017-10-02T13:08:09Z

@helmut64 maybe my description in the introductory PR #3181 helps

helmut64 · 2017-10-02T13:39:30Z

@ohagendorf Danke, now I understand, the PinMap table as an unique index for each pin therfore we use alternate names for multiple pin options. Working on it.

bcostm · 2017-10-02T13:41:39Z

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC/PeripheralPins.c

+
+__weak const PinMap PinMap_UART_RX[] = {
+//    {PA_3,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},


Can you add a comment:
// Connected to STDIO_UART_RX

bcostm · 2017-10-02T13:56:53Z

Thanks @helmut64
Concerning the pins PC_5 and PD_2, you have to remove them because they are not present on the NUCLEO_L433RC_P. Your original file version was correct. I thought you were working on the NUCLEO_L433RC (without the '-P'). Sorry about that.

helmut64 · 2017-10-02T19:11:48Z

@bcostm I keep the PC_5, PD_2 because I use the STM433RCT for my projects. This is not hurting and helps me.
I added the _ALT mappings, this is a good solution.
All your feedback has been incorporated.

helmut64 · 2017-10-03T11:57:23Z

@bcostm I reviewed the targets.json file for our new target, here are some questions:
a) "bootloader_supported": true
This is missing, it is included in the NUCLEO_L476RG/NUCLEO_L486RG targets, I don't see any reason not to enable it as well for the 433RC_P board. Any ideas?

b) SERIAL_ASYNCH
Again there is any reason this should be disabled, because the 433 uses the same serial as the other L4 MCUs. Maybe there is a difference in the DMA channels.

c) "release_versions": ["2", "5"],
Is this correct, I just copied it from the 432KC as a template.

Your advise will be appreciated.

… defines

overwrites for different MCU kinds.

…TX/RX

added connected to STDIO_UART_XX comments

Comment out the STM32L433_100PINS defined because PD_2 is already used in the PeripheralPins.c, otherwise it will not compile

Added SERIAL_ASYNCH into STM32L432KC target, it is now identical with the STM32L433RC_P and other STM L4 targets.

…32KC

MBED_APP_START/MBED_APP_SIZE variables

MORPHO headers

…4/mbed-os into NUCLEO_STM32L433_SUPPORT

helmut64 · 2017-11-26T18:52:20Z

I did the rebase. I hope that this is now good.
I compiled the branch, it contains my changes.

0xc0170 · 2017-11-27T08:00:01Z

@helmut64 The branch shows here 250+ commits, it should contain only your changes.

helmut64 · 2017-11-27T09:43:35Z

@0xc0170 Hello Martin, than I will create a new branch, redo the changes and push it.
Will this be working for you?

0xc0170 · 2017-11-27T12:02:29Z

@0xc0170 Hello Martin, than I will create a new branch, redo the changes and push it.
Will this be working for you?

Whatever works for you. It would be good to resolve it here via rebase but a new branch also work. This would be closed and new PR opened.

helmut64 · 2017-11-27T14:55:08Z

I created a new pull request #5591 branch NUCLEO_STM32L433_NEW

helmut64 mentioned this pull request Oct 1, 2017

STM32L4 combining support for L431xx, L432xx and L433xx devices #4144

Closed

0xc0170 added the needs: review label Oct 2, 2017

bcostm reviewed Oct 2, 2017

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tools/export/sw4stm32/__init__.py Outdated

'NUCLEO_L433RC':

{

'name': 'NUCLEO-L433RC',

'mcuId': 'STM32L433RCUx'

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STM32L433RCTxP

helmut64 changed the title ~~New support for the STM NUCLEO_L433RC board~~ New support for the STM NUCLEO_L433RC-P board Oct 2, 2017

bcostm reviewed Oct 2, 2017

View reviewed changes

helmut64 added 22 commits November 26, 2017 18:16

Copied TARGET_STM32L432 to TARGET_STM32L433

9ea50c6

Added proper Pin and Peripheral defines for the STM433RC Nucleo.

247754c

Added stm32l433xx.h defined STM32L433xx

bb0ce82

Renmed 432 startup files to 433

8c8d7d9

Updated startup.s files for the 433 vectors (ARM/GCC/IAR)

3989123

disabled CAN define like in other STM platforms, we use CAN1 instead

0da13bc

Added NUCLEO_L433RC into build targets

03bb435

Added support for 433 100 pins versions and 48 pin versions via extra…

91bb04c

… defines

Changed PinMap mapping to be weak linking. This allows

98517a8

overwrites for different MCU kinds.

Disabled LPUART on PA_2/PA_3 because this is in conflict with SERIAL_…

9d491c8

…TX/RX

Updated 433RC name to accurate names

6a8155f

Added missing PC5, PD2 pins,

340c99a

added connected to STDIO_UART_XX comments

Renamed folder TARGET_NUCLEO_L433RC to TARGET_NUCLEO_L433RC_P

7800a36

removed the TIM6/TIM7 TODOs, no PWM support this this.

f22fc61

Comment out the STM32L433_100PINS defined because PD_2 is already used in the PeripheralPins.c, otherwise it will not compile

Removed illegal entered char

a5ba0fc

Added the alternative pin names and adjusted the mappings.

524356d

Enabled SERIAL_ASYNCH for the NUCLEO 433RC target

0391b4e

Added bootloader support for STM32L433RC_P and STM32L432KC targets

6b54a6e

Added SERIAL_ASYNCH into STM32L432KC target, it is now identical with the STM32L433RC_P and other STM L4 targets.

Added NVIC_FLASH_VECTOR_ADDRESS into system_clock.c for 433RC_P and 4…

c695e01

…32KC

Added linker updated files for 433RC and 432KC to use the

d406d76

MBED_APP_START/MBED_APP_SIZE variables

Added MORPHO into NUCLEO_L433RC_P target because it has

428040d

MORPHO headers

Merge branch 'NUCLEO_STM32L433_SUPPORT' of https://github.com/helmut6…

37cc297

…4/mbed-os into NUCLEO_STM32L433_SUPPORT

helmut64 mentioned this pull request Nov 27, 2017

Support the STM NUCLEO_L433RC-P board #5591

Merged

0xc0170 closed this Nov 27, 2017

0xc0170 removed the needs: work label Nov 27, 2017

New support for the STM NUCLEO_L433RC-P board #5230

New support for the STM NUCLEO_L433RC-P board #5230

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