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2 changes: 2 additions & 0 deletions ddprof-lib/src/main/cpp/arch_dd.h
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,8 @@

#include <stddef.h>

constexpr int DEFAULT_CACHE_LINE_SIZE = 64;

static inline long long atomicInc(volatile long long &var,
long long increment = 1) {
return __sync_fetch_and_add(&var, increment);
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8 changes: 5 additions & 3 deletions ddprof-lib/src/main/cpp/spinLock.h
Original file line number Diff line number Diff line change
Expand Up @@ -21,15 +21,17 @@

// Cannot use regular mutexes inside signal handler.
// This lock is based on CAS busy loop. GCC atomic builtins imply full barrier.
class SpinLock {
class alignas(DEFAULT_CACHE_LINE_SIZE) SpinLock {
private:
// 0 - unlocked
// 1 - exclusive lock
// <0 - shared lock
volatile int _lock;

char _padding[DEFAULT_CACHE_LINE_SIZE - sizeof(_lock)];
public:
constexpr SpinLock(int initial_state = 0) : _lock(initial_state) {}
constexpr SpinLock(int initial_state = 0) : _lock(initial_state), _padding() {
static_assert(sizeof(SpinLock) == DEFAULT_CACHE_LINE_SIZE);
}

void reset() { _lock = 0; }

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