[None][chore] optimize kv cache transfer for context TEP and gen DEP

[chuangz0]

Summary by CodeRabbit

• Optimization
  • When context TEP and gen DEP, each dp rank of gen will request kv cache from context tp rank0 before.
    We changed it so that dp rank will request kv cache from context tp_rank = gen_dp_rank%tp_num.
• Tests
  • Updated test assertions to reflect new cache sending logic and improved test readability.

Description

Test Coverage

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[coderabbitai]

📝 Walkthrough

Walkthrough

The changes update the internal logic of cache formatting and selection in the batch manager, specifically refining how data parallel and tensor parallel ranks are considered when attention data parallelism is enabled. Adjustments are made to both production code and related test assertions, but no public interfaces are altered.

Changes

Cohort / File(s)	Change Summary
CacheFormatter logic update cpp/tensorrt_llm/batch_manager/cacheFormatter.cpp	Modified needSendCache and pickRecvConnections to factor in data parallel rank when attention DP is enabled, changing selection conditions for sending cache and picking receive connections.
MLACacheFormatter logic update cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp	Refined pickRecvConnections and needSendCache to introduce and use data parallel rank and tensor parallel group calculations, adjusting cache send/receive logic for attention DP scenarios.
Test expectation and formatting cpp/tests/batch_manager/cacheTransceiverTest.cpp	Swapped two test assertions for expected cache send behavior under context DP, and made minor formatting changes for readability.

Sequence Diagram(s)

sequenceDiagram
    participant Sender as CacheSender
    participant Receiver as CacheReceiver
    participant Formatter as CacheFormatter/MLACacheFormatter

    Sender->>Formatter: needSendCache(destRank, ...)
    Formatter->>Sender: Returns true/false based on DP/TP logic

    Receiver->>Formatter: pickRecvConnections(...)
    Formatter->>Receiver: Returns list of connections based on DP/TP logic

Loading

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~8 minutes

Suggested reviewers

• chzblych
• pcastonguay
• HuiGao-NV
• Shixiaowei02
• achartier

Note

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📜 Recent review details

Configuration used: .coderabbit.yaml
Review profile: CHILL
Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 907c180 and 152fd01.

📒 Files selected for processing (3)

• cpp/tensorrt_llm/batch_manager/cacheFormatter.cpp (2 hunks)
• cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp (3 hunks)
• cpp/tests/batch_manager/cacheTransceiverTest.cpp (2 hunks)

🧰 Additional context used

🧠 Learnings (2)

📓 Common learnings

Learnt from: amitz-nv
PR: NVIDIA/TensorRT-LLM#5616
File: tensorrt_llm/executor/worker.py:375-384
Timestamp: 2025-07-17T09:01:27.402Z
Learning: In tensorrt_llm/executor/worker.py, the LoRA adapter cache optimization logic that checks `is_adapter_in_cpu_cache()` and conditionally passes None for weights/config has a known race condition issue that cannot be solved with simple error handling or verification checks. This is a known limitation that requires a more comprehensive solution.

📚 Learning: in tensorrt_llm/executor/worker.py, the lora adapter cache optimization logic that checks `is_adapte...

Learnt from: amitz-nv
PR: NVIDIA/TensorRT-LLM#5616
File: tensorrt_llm/executor/worker.py:375-384
Timestamp: 2025-07-17T09:01:27.402Z
Learning: In tensorrt_llm/executor/worker.py, the LoRA adapter cache optimization logic that checks `is_adapter_in_cpu_cache()` and conditionally passes None for weights/config has a known race condition issue that cannot be solved with simple error handling or verification checks. This is a known limitation that requires a more comprehensive solution.

Applied to files:

• cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp

⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)

• GitHub Check: Pre-commit Check

🔇 Additional comments (8)

cpp/tests/batch_manager/cacheTransceiverTest.cpp (3)

460-460: LGTM! Improved test readability.

The blank line additions around verifyContext calls enhance code readability without affecting functionality.

Also applies to: 463-463, 468-468

---

569-569: LGTM! Test assertion updated to reflect refined cache sending logic.

The change from expectNeedSend: true to false for contextRank 0 → generationRank 1 correctly reflects the updated cache formatter logic that now incorporates data parallel rank considerations when determining cache sending decisions.

---

575-575: LGTM! Complementary test assertion update.

The change from expectNeedSend: false to true for contextRank 1 → generationRank 1 complements the previous assertion change and correctly validates the updated cache sending logic that considers data parallel ranks in cache transfer decisions.

cpp/tensorrt_llm/batch_manager/cacheFormatter.cpp (2)

92-94: LGTM! Proper integration of destination DP rank in cache sending logic.

The changes correctly incorporate destination data parallel rank (destDPRank) considerations into the cache sending decision. The logic appropriately:

1. Extracts the destination DP rank when attention DP is enabled (line 92)
2. Uses it in the modulo comparison to determine if cache should be sent (line 94)

This ensures cache sending decisions properly account for both source and destination DP rank configurations, which is essential for correct data parallel cache transfers.

---

131-131: LGTM! Consistent DP rank integration in receive connection selection.

The changes properly mirror the sending logic by incorporating self data parallel rank (selfDPRank) considerations into connection selection for receiving. The implementation:

1. Extracts the self DP rank when attention DP is enabled (line 131)
2. Uses it in the modulo comparison for connection filtering (line 136)

This maintains logical consistency between the sending (needSendCache) and receiving (pickRecvConnections) functions, ensuring proper coordination of cache transfers in data parallel scenarios.

Also applies to: 136-136

cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp (3)

48-53: LGTM: Proper DP rank integration for connection selection.

The logic correctly incorporates data parallel rank considerations when attention DP is enabled, falling back to rank 0 when disabled to preserve original behavior. The offset calculation properly distributes connections across DP groups.

---

91-92: Same verification needed for non-DP branch.

The same DP rank comparison logic is applied in the non-DP self configuration branch. This should be verified along with the DP-enabled branch above.

---

63-80: Please manually verify the DP-aware duplication logic in needSendCache

I wasn’t able to find another reference for this pattern in the codebase, so it’s not conclusive that the destDPRank comparison is correct. Specifically, double-check that you really want to compare against the data-parallel rank (rather than a tensor-parallel index) when deciding which KV-cache partitions to send.

Key locations to review in cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp:

• Lines 79–80 (DP branch):
  return selfTPrankINDPGroup % dupHeadFactor == destDPRank;
• Lines 91–92 (non-DP branch):
  return selfTpRank % dupHeadFactor == destDPRank;

Make sure that:
• dupHeadFactor = #self_heads_per_DP_group / #dest_heads_per_DP_group
• destDPRank correctly identifies which slice of the duplicated heads this recipient should get
• For all combinations of mTensorParallelism and mDPsize, every dest DP rank receives exactly its intended subset of heads

If in doubt, adding unit or integration tests over multiple DP sizes (e.g. DPsize > dupHeadFactor, DPsize < dupHeadFactor) will surface any gaps.

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[chuangz0]

/bot run --add-multi-gpu-test

[tensorrt-cicd]

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[tensorrt-cicd]

PR_Github #14260 [ run ] completed with state SUCCESS
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