[None][fix] Make TP working for Triton MOE (in additional to EP we are using) #6722
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📝 WalkthroughWalkthroughThe changes introduce enhanced support for tensor parallelism and hardware-specific constraints in the MXFP4 Fused MoE module, including padding and slicing of weights, scales, and activations. Test coverage is expanded to new tensor shapes and parallel configurations, and test parameterization is updated to reflect these capabilities. Changes
Sequence Diagram(s)sequenceDiagram
participant User
participant Module
participant TritonMXFP4FusedMoEMethod
participant GPU
User->>Module: Calls apply(x, router_logits)
Module->>TritonMXFP4FusedMoEMethod: apply(x, router_logits)
TritonMXFP4FusedMoEMethod->>TritonMXFP4FusedMoEMethod: _maybe_pad_activation(x, in_dim_padding_offset)
TritonMXFP4FusedMoEMethod->>GPU: GEMM 1 (using padded x and weights)
TritonMXFP4FusedMoEMethod->>TritonMXFP4FusedMoEMethod: _maybe_pad_activation(intermediate, out_dim_padding_offset)
TritonMXFP4FusedMoEMethod->>GPU: GEMM 2 (using padded intermediate and weights)
TritonMXFP4FusedMoEMethod->>Module: Returns output
Estimated code review effort🎯 4 (Complex) | ⏱️ ~40 minutes Suggested reviewers
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Actionable comments posted: 0
🧹 Nitpick comments (1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py (1)
1012-1056: Good implementation of padding logic for hardware constraints.The
_maybe_pad_weight_and_scalefunction correctly handles both Hopper-specific out-dimension padding and TP-related in-dimension padding with proper offset management. The assertions provide good validation.Consider adding a docstring to document the padding requirements and the purpose of
in_dim_padding_offset.
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📒 Files selected for processing (3)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py(11 hunks)tests/integration/defs/accuracy/test_llm_api_pytorch.py(1 hunks)tests/unittest/_torch/modules/test_fused_moe.py(1 hunks)
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Files:
tests/unittest/_torch/modules/test_fused_moe.pytests/integration/defs/accuracy/test_llm_api_pytorch.pytensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py
**/*.{cpp,h,hpp,cc,cxx,cu,py}
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Files:
tests/unittest/_torch/modules/test_fused_moe.pytests/integration/defs/accuracy/test_llm_api_pytorch.pytensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py
🧠 Learnings (1)
📚 Learning: 2025-07-28T17:06:08.621Z
Learnt from: moraxu
PR: NVIDIA/TensorRT-LLM#6303
File: tests/integration/test_lists/qa/examples_test_list.txt:494-494
Timestamp: 2025-07-28T17:06:08.621Z
Learning: In TensorRT-LLM testing, it's common to have both CLI flow tests (test_cli_flow.py) and PyTorch API tests (test_llm_api_pytorch.py) for the same model. These serve different purposes: CLI flow tests validate the traditional command-line workflow, while PyTorch API tests validate the newer LLM API backend. Both are legitimate and should coexist.
Applied to files:
tests/integration/defs/accuracy/test_llm_api_pytorch.py
🪛 Ruff (0.12.2)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py
1091-1091: Line too long (141 > 120)
(E501)
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- GitHub Check: Pre-commit Check
🔇 Additional comments (8)
tests/unittest/_torch/modules/test_fused_moe.py (1)
1301-1305: LGTM! Good expansion of test coverage for tensor parallelism.The new test parameters with hidden_size=2880 and varying intermediate sizes are well-chosen to validate the enhanced TP support and padding/slicing logic in the Triton MoE implementation.
tests/integration/defs/accuracy/test_llm_api_pytorch.py (1)
2469-2474: LGTM! Good addition of TP=2 test configurations.The rename to
test_w4_multigpubetter reflects the expanded scope of the test, and the addition of TP=2 configurations properly validates the PR's tensor parallelism improvements for Triton MOE.tensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py (6)
629-654: LGTM! Good hardware compatibility handling for NVIDIA H20.The addition of shape validation and the conditional use of StridedLayout for H20 GPUs is a good workaround for hardware-specific issues. The assertions will help catch shape mismatches early.
674-676: LGTM! Appropriate padding multiples for GPU memory alignment.The padding multiples of 128 for input dimension and 256 for output dimension align with GPU memory access patterns and are necessary for proper hardware utilization.
687-708: LGTM! Improved scale tensor handling for tensor parallelism.The change to use full-size scale tensors with
ceil_divfor proper block size handling is cleaner and correctly handles cases where dimensions aren't perfectly divisible by the block size (32). The deferred slicing approach is more maintainable.
1059-1096: LGTM! Robust tensor parallel slicing for scales.The scale slicing logic correctly handles partial blocks when TP boundaries don't align with mxfp4's 32-element blocks. The
w2_tp_offsettracking for partial block handling is a clever solution to maintain correct alignment.
1168-1179: LGTM! Consistent activation padding for tensor parallelism.The
_maybe_pad_activationfunction correctly applies the same padding logic to activations as used for weights, ensuring proper alignment for matrix multiplication operations.
1193-1193: LGTM! Correct application of activation padding.The activation padding is properly applied before each GEMM operation, with appropriate offset handling for the second GEMM to account for TP partitioning.
Also applies to: 1248-1248
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Signed-off-by: Dongfeng Yu <[email protected]> Add draft Signed-off-by: Dongfeng Yu <[email protected]> Fix Signed-off-by: Dongfeng Yu <[email protected]> Fix Signed-off-by: Dongfeng Yu <[email protected]> Fix Signed-off-by: Dongfeng Yu <[email protected]> Fix Signed-off-by: Dongfeng Yu <[email protected]>
Signed-off-by: Dongfeng Yu <[email protected]>
Signed-off-by: Dongfeng Yu <[email protected]>
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…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]> Signed-off-by: Wangshanshan <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]> Signed-off-by: Wangshanshan <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]> Signed-off-by: Wangshanshan <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]>
…e using) (NVIDIA#6722) Signed-off-by: Dongfeng Yu <[email protected]> Signed-off-by: Wangshanshan <[email protected]>
Tested against test_w4_multigpu[{tp,ep,dp} * {2, 4}-TRITON]
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