[https://nvbugs/5481385][fix] Fix max_seq_len in cuda graph warmup and intermediate_size in fused_moe_deepgemm #7345
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…oe_deepgemm. Signed-off-by: Fanrong Li <[email protected]>
lfr-0531
requested review from
litaotju,
Barry-Delaney,
peaceh-nv,
HuiGao-NV and
pengbowang-nv
📝 WalkthroughWalkthroughAdjusts internal dimensions in fused MoE DeepGEMM to use per-partition intermediate size, affecting workspace and forward computations. Adds an extra clamp in the CUDA graph warmup path to respect max_position_embeddings when deriving dummy request token length. No public API changes. Changes
Sequence Diagram(s)sequenceDiagram
autonumber
participant ME as ModelEngine
participant MC as ModelConfig
participant PC as pretrained_config
ME->>ME: Compute token_num from available tokens and max_seq_len
ME->>MC: Access pretrained_config
alt max_position_embeddings present
MC-->>ME: PC.max_position_embeddings
ME->>ME: Clamp token_num to min(token_num, max_position_embeddings - draft_len)
else
Note over ME: No additional clamp
end
ME->>ME: Build dummy CUDA graph warmup request with final token_num
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~20 minutes Possibly related PRs
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📒 Files selected for processing (2)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py(3 hunks)tensorrt_llm/_torch/pyexecutor/model_engine.py(1 hunks)
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📓 Path-based instructions (2)
**/*.py
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Files:
tensorrt_llm/_torch/pyexecutor/model_engine.pytensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py
**/*.{cpp,cc,cxx,cu,h,hpp,hh,hxx,cuh,py}
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Files:
tensorrt_llm/_torch/pyexecutor/model_engine.pytensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py
🧠 Learnings (3)
📓 Common learnings
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Learnt from: sklevtsov-nvidia
PR: NVIDIA/TensorRT-LLM#3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
PR: NVIDIA/TensorRT-LLM#3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py
🧬 Code graph analysis (2)
tensorrt_llm/_torch/pyexecutor/model_engine.py (3)
tensorrt_llm/_torch/attention_backend/trtllm.py (2)
max_seq_len(558-568)max_seq_len(571-575)tensorrt_llm/_torch/models/checkpoints/base_weight_mapper.py (1)
model(162-165)tensorrt_llm/_torch/pyexecutor/cuda_graph_runner.py (1)
draft_len(56-57)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
intermediate_size(226-226)tensorrt_llm/quantization/utils/fp8_utils.py (1)
ceil_div(10-21)
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🔇 Additional comments (3)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py (3)
412-431: Using per-partition intermediate size in workspace is correctSwitching to intermediate_size_per_partition keeps workspace sizing aligned with expert sharding; fp8_dim and workspace_1 now safely cover both hidden and intermediate paths. LGTM.
565-568: h1 K-dimension should be per-partition intermediate_size × 2Good fix. This matches w3_w1 concatenation shape and prevents over-allocation when experts are partitioned.
581-585: Quant/scale dims aligned to per-partition intermediate_sizeUpdating act_input_fp8 stride and scale_k to intermediate_size_per_partition removes mismatches in the second GEMM path. Looks correct.
lfr-0531
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lfr-0531
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…d intermediate_size in fused_moe_deepgemm (NVIDIA#7345) Signed-off-by: Fanrong Li <[email protected]> Co-authored-by: Tao Li @ NVIDIA <[email protected]>
…oe_deepgemm.
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