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@hyukn hyukn commented Sep 16, 2025

Summary by CodeRabbit

  • New Features

    • Runtime-selectable all-reduce strategy: reduction method now adapts to GPU capability, with a reliable fallback on older architectures.
  • Bug Fixes

    • Improved stability and performance on older GPUs by choosing an appropriate reduction strategy automatically.
    • Existing tensor mapping behavior preserved to avoid changes in distribution patterns.

Description

Pass allreduce strategy from the model config and force NCCL on pre-Blackwell arch due to perf regression observed on A100/H100.

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Please review the following before submitting your PR:

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  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

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  • Documentation updated as needed

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@hyukn hyukn requested a review from a team as a code owner September 16, 2025 11:32
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📝 Walkthrough

Walkthrough

Add AllReduceStrategy export and pass a strategy argument when constructing AllReduce in Llama4DecoderLayer.__init__; the strategy is selected at runtime depending on get_sm_version() (fallback to AllReduceStrategy.NCCL for older SM versions). A TODO comment notes this is a temporary perf workaround.

Changes

Cohort / File(s) Change summary
Llama decoder comms
tensorrt_llm/_torch/models/modeling_llama.py
- Import AllReduceStrategy from tensorrt_llm._torch.distributed
- AllReduce now constructed with strategy=... and mapping=... (strategy chosen as model_config.allreduce_strategy if get_sm_version() >= 100 else AllReduceStrategy.NCCL)
- Added TODO comment noting temporary fix for pre-Blackwell perf regressions
Public API exports
tensorrt_llm/_torch/distributed/...
- AllReduceStrategy added to public exports (constructor signature of AllReduce now accepts strategy)

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant App as App
  participant L4 as Llama4DecoderLayer.__init__
  participant SM as GPU SM (get_sm_version)
  participant AR as AllReduce

  App->>L4: __init__(model_config)
  L4->>SM: get_sm_version()
  SM-->>L4: sm_version
  alt sm_version >= 100
    L4->>AR: new AllReduce(strategy=model_config.allreduce_strategy, mapping=model_config.mapping)
  else sm_version < 100
    L4->>AR: new AllReduce(strategy=AllReduceStrategy.NCCL, mapping=model_config.mapping)
  end
  AR-->>L4: AllReduce instance
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Pre-merge checks

❌ Failed checks (2 warnings)
Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. You can run @coderabbitai generate docstrings to improve docstring coverage.
Description Check ⚠️ Warning The PR description is minimal and does not follow the repository template: it is missing the required templated PR title line, the Test Coverage section is empty, and the PR Checklist items are not completed. The Description is a single sentence and omits important reviewer-facing details such as measured perf data, exact SM/GPU targets, and the public API change (AllReduce constructor signature and added AllReduceStrategy). Because of these omissions, reviewers cannot fully assess impact, test coverage, or migration needs. Add the required templated PR title at the top and expand the Description to explain what changed, why, and include concrete perf/regression evidence and exact target architectures/SM versions; explicitly document the public API change (AllReduce signature now accepts strategy and AllReduceStrategy was added) and any migration or compatibility implications. Populate the Test Coverage section with the unit/integration tests or CI stages that validate runtime strategy selection and AR-fusion disablement and include links to relevant CI/perf runs. Complete the PR Checklist and, if applicable, update docs/CHANGELOG/CODEOWNERS so reviewers can verify functional and non-functional impacts.
✅ Passed checks (1 passed)
Check name Status Explanation
Title Check ✅ Passed The title succinctly and accurately captures the primary change: passing the allreduce strategy and forcing an NCCL fallback on pre-Blackwell architectures. It is a single, clear sentence that aligns with the PR objectives and the raw_summary (updating the AllReduce call site and choosing NCCL for older SMs). The included bug reference and [fix] tag act as acceptable metadata and do not obscure the intent.

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hyukn commented Sep 16, 2025

/bot run

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PR_Github #18788 [ run ] triggered by Bot

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Actionable comments posted: 1

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)
tensorrt_llm/_torch/models/modeling_llama.py (1)

1-3: Missing required NVIDIA Apache‑2.0 header.

Per repo guidelines, prepend the current-year header to this file.

Apply:

+# Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
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🧠 Learnings (1)
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
PR: NVIDIA/TensorRT-LLM#6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.

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  • tensorrt_llm/_torch/models/modeling_llama.py
🧬 Code graph analysis (1)
tensorrt_llm/_torch/models/modeling_llama.py (2)
tensorrt_llm/_torch/distributed/ops.py (1)
  • AllReduce (362-491)
tensorrt_llm/_utils.py (1)
  • get_sm_version (681-683)
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🔇 Additional comments (1)
tensorrt_llm/_torch/models/modeling_llama.py (1)

649-652: Require explicit AllReduce.strategy or a safe ModelConfig default

Script output shows AllReduce() invocations without a strategy kwarg at:

  • ./tensorrt_llm/_torch/distributed/ops.py:287
  • ./tensorrt_llm/_torch/distributed/ops.py:362
  • ./tensorrt_llm/_torch/distributed/ops.py:424
  • ./tensorrt_llm/_torch/distributed/ops.py:494
  • ./tensorrt_llm/_torch/models/modeling_deepseekv3.py:688
  • ./tensorrt_llm/_torch/models/modeling_llama.py:454
  • ./tensorrt_llm/_torch/models/modeling_qwen3_moe.py:206
  • ./tests/unittest/_torch/auto_deploy/unit/multigpu/transformations/library/test_collective_fusion.py:20
  • ./tests/unittest/_torch/multi_gpu/test_allreduce.py:129
  • ./tests/unittest/_torch/multi_gpu/test_allreduce.py:340
  • ./tests/unittest/_torch/multi_gpu/test_allreduce.py:502
  • ./tests/unittest/_torch/multi_gpu/test_user_buffers.py:695
  • ./tests/unittest/_torch/multi_gpu/test_user_buffers.py:696
  • ./tests/unittest/_torch/multi_gpu/test_user_buffers.py:697

Action: update these call sites to pass strategy (e.g., strategy=model_config.allreduce_strategy or an explicit AllReduceStrategy like AUTO), or ensure ModelConfig supplies that safe default.

⛔ Skipped due to learnings
Learnt from: timlee0212
PR: NVIDIA/TensorRT-LLM#6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.

@hyukn hyukn changed the title [None][fix] Pass allreduce strategy and disable AR fusion due to perf regression on preBlackwell [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on preBlackwell Sep 16, 2025
@hyukn hyukn changed the title [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on preBlackwell [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on pre-Blackwell Sep 16, 2025
…fusion due to perf regression on preBlackwell.

Signed-off-by: Yukun He <[email protected]>
@hyukn hyukn force-pushed the fix/llama3_allreduce_strategy branch from 580a733 to b666707 Compare September 16, 2025 12:13
@hyukn hyukn changed the title [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on pre-Blackwell [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on pre-Blackwell arch Sep 16, 2025
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hyukn commented Sep 16, 2025

/bot run

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PR_Github #18794 [ run ] triggered by Bot

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PR_Github #18788 [ run ] completed with state ABORTED
LLM/release-1.0/L0_MergeRequest_PR #396 (Blue Ocean) completed with status: ABORTED

@hyukn hyukn changed the title [https://nvbugs/5517023][fix] Pass allreduce strategy and disable AR fusion due to perf regression on pre-Blackwell arch [https://nvbugs/5517023][fix] Pass allreduce strategy and force NCCL on pre-Blackwell arch Sep 16, 2025
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PR_Github #18794 [ run ] completed with state SUCCESS
/LLM/release-1.0/L0_MergeRequest_PR pipeline #399 completed with status: 'FAILURE'

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hyukn commented Sep 17, 2025

/bot run

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PR_Github #18848 [ run ] triggered by Bot

@litaotju litaotju added the Release Blocker PRs that blocking the final release build or branching out the release branch label Sep 17, 2025
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PR_Github #18848 [ run ] completed with state SUCCESS
/LLM/release-1.0/L0_MergeRequest_PR pipeline #403 completed with status: 'SUCCESS'

@Superjomn Superjomn merged commit 88fe78e into NVIDIA:release/1.0 Sep 17, 2025
8 checks passed
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 17, 2025
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 17, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 17, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
litaotju added a commit to litaotju/TensorRT-LLM that referenced this pull request Sep 17, 2025
…ce NCCL on pre-Blackwell arch (NVIDIA#7768)"

This reverts commit 88fe78e.

Signed-off-by: Tao Li <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 17, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 18, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 18, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 18, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 19, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 19, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 19, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 19, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
chzblych pushed a commit that referenced this pull request Sep 22, 2025
…on pre-Blackwell arch (#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
JunyiXu-nv pushed a commit to JunyiXu-nv/TensorRT-LLM that referenced this pull request Sep 22, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
nv-lschneider pushed a commit to nv-lschneider/TensorRT-LLM that referenced this pull request Sep 22, 2025
…on pre-Blackwell arch (NVIDIA#7768)

Signed-off-by: Yukun He <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
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