Adjust SkylakeX GEMM3M parameters, add an AVX512 STRMM kernel and fix performance bugs in AVX2 s/c/z GEMM

[wjc404]

PS: I forgot to change SKX GEMM3M parameters when I added those kernels 2 month ago, sorry for that. I fix it in this PR.

[wjc404]

The STRMM kernel passed 1-thread reliability test.

[marxin]

The STRMM kernel passed 1-thread reliability test.

Can you please rather send the results directly via a direct text comment instead of a screenshot?

[wjc404]

@marxin I've closed those terminals running strmm tests, so the text output cannot be retrieved. The test program was attached in a comment of PR #2361 .
BTW have you tested 1-thread and 8-thread SGEMM performance of MKL, OpenBLAS-0.3.7 and OpenBLAS-0.3.8 on r7-2700X?

[marxin]

@marxin I've closed those terminals running strmm tests, so the text output cannot be retrieved. The test program was attached in a comment of PR #2361 .

Sure, I mean for the next time you'll paste some results. Thanks.

[TiborGY]

The STRMM kernel passed 1-thread reliability test.

Can you please rather send the results directly via a direct text comment instead of a screenshot?

Just out of curiosity, why do you prefer text?

[marxin]

Just out of curiosity, why do you prefer text?

I see the screenshots scaled and I need to click to see a full screen. Moreover, one can't copy commands from screenshots. And I also don't see how were the tests run, it's scrolled down.

[wjc404]

The new AVX2 SGEMM kernel passed 2 reliability tests (using the test program attached in PR #2300 ).
testlog_avx2_serial_sgemm_20190223_epycrome.txt

testlog_avx2_serial_sgemm_20190223_epycrome_2.txt

[wjc404]

The modified AVX512 SGEMM kernel passed an 1-thread test.

testlog_aliyun_sgemm_avx512_1thread.txt

[wjc404]

Recently I found a performance issue on Haswell-EP and Broadwell-EP processors: the execution of register-to-register vector permutation instructions can interfere with that of FMA instructions (which is not an issue on Skylake-client or Zen2 processors). Changing vector permutation instructions to memory-to-register type can avoid this issue. The 1-thread performances of CGEMM and ZGEMM rose about 15% (to 98% MKL2018) on these processors after the changes in this PR.

[martin-frbg]

that is an interesting quirk of the EP models - please advise if it would make coding easier for you if these were detected as a separate TARGET type, or with a specific #define available at compile time ?

[wjc404]

Probably not necessary in my opinion. The usage of vector permutation instructions in level3 kernels is not common.

[marxin]

Recently I found a performance issue on Haswell-EP and Broadwell-EP processors: the execution of register-to-register vector permutation instructions can interfere with that of FMA instructions (which is not an issue on Skylake-client or Zen2 processors).

May I please ask how did you notice that? It's an interesting observation.

About the introduction of the new sgemm_kernel_8x4_haswell_2.c kernel: Can you please describe how is the implementation different?

[wjc404]

Remove redundant prefetch instructions in avx2 c/z gemm kernels (they actually do a little harm).

[wjc404]

@marxin I found it accidentally in a test, when I received significant performance gain after changing those permute instructions. I confirmed that with the test program in "test_fma_perm_instflow.zip".
In the kernel "sgemm_kernel_8x4_haswell_2.c", I reordered the calculation steps, rearranged 2 adjacent 8rowX12col stores (to matrix C) to 2 16rowX6col stores, while maintaining the same reading rate from L3 cache.
In a 16rowX6col write to a block of column-major matrix C in 8-way set associative cache, there's little risk of conflict misses which could occur in a 8rowX12col write.

[marxin]

In the kernel "sgemm_kernel_8x4_haswell_2.c", I reordered the calculation steps, rearranged 2 adjacent 8rowX12col stores (to matrix C) to 2 16rowX6col stores, while maintaining the same reading rate from L3 cache.

Nice. That seems smart.
Btw. I've spent some time with reading of the Anatomy of High-Performance Matrix Multiplication - 2008 and also the new kernels you written. I see it still quite difficult to understand the implementation. Is there anything that can help me to understand it? Thanks.