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fpga.yaml: add example 'with:' VERILOG_DEFINES and YOSYS_ARGS #6

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fpga.yaml: add example 'with:' VERILOG_DEFINES and YOSYS_ARGS #6

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5 changes: 5 additions & 0 deletions .github/workflows/fpga.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -17,3 +17,8 @@ jobs:

- name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@ttsky25b
with:
# example values: MY_CUSTOM_DEFINE ANOTHER_CUSTOM_DEFINE=VALUE
VERILOG_DEFINES:
# advanced use only, command line arguments passed to yosys for synthesis
YOSYS_ARGS: