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Vaibhav-Gunthe/readme.md

Hi 👋, I'm Vaibhav Gunthe

Aspiring VLSI Design Engineer | Verilog & RTL Design Enthusiast

💫 About Me

🌌 I’m currently working on a Neural Processing Unit (NPU) using Verilog HDL and RTL design flow
🤝 I’m looking to collaborate on open-source VLSI/RTL design projects
🧠 I’m currently learning Computer Architecture, FSM Design, and System Verilog
💬 Ask me about Verilog, RTL modeling, FSMs, and logic synthesis
⚡ Fun fact: I can simulate a 8-bit ALU before finishing my coffee

🛠️ Tech Stack

Verilog SystemVerilog Vivado C C++ Python

📊 GitHub Stats

GitHub Stats GitHub Streak Stats

📫 Connect With Me

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  1. Verilog-Projects Verilog-Projects Public

    A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

    Verilog 4