Porting verilog-ethernet to KR260

[vmayoral]

(This first comment will be updated as the porting efforts evolve and will summarize results so that others can benefit from it.)

Hi @alexforencich and all,

First off, congrats for an impresive piece. The project is not only well maintained but has grown a significant community around it. Very impressive. Congrats and kudos to @alexforencich. I'm currently involved into a project considering to port Corundum into the AMD KR260. This board leverages an AMD Zynq UltraScale+ SoC and exposes various Ethernet (Gb RGMII PL and PS) interfaces and an SFP+ connector which makes it a pretty target for benchmarking.

For now, our endeavour aims to bring ethernet-verilog up to speed into the KR260 and produce some latency performance benchmarking comparisons by leveraging a low overhead and real-time capable tracer (we'll be using LTTng on the PS side, and Vitis Profiler on the PL side).

By doing so, we hope to contribute to this project by 1) bringing a usable port of ethernet-verilog (Corundum) for a popular FPGA SoC SOM, 2) provide a fair and reproducible latency benchmark that compares UDP/IP networking performance (L1-L2-L3-L4) across various setups.

                                               Media Access
      Transport (UDP)      Network  (IP)       Control (MAC)                   Physical layer (PHY)        Media Dependent Interface (MDI)

   +----------------+  +----------------+   +------------------+  +---------------------------------------+   +-------------------+
   |                |  |                |   |                  |  |     PCS: Physical      PMA: Physical  |   |                   |
   |                |  |                |   |                  |  |     Coding             Medium         |   |    +---------+    |
   |                |  |                |   |                  |  |     Sublayer           Attachment     |   |    |         |    |
   |                |  |                |   |                  |  |    +--------------+    +-----------+  |   |    |         |    |
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |         |    |
<---+              <----+              <-----+                 <----------+encoder<---------+serializer<-----------+         |    |    +---------+
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |   SFP+  +<-------->  cable  |
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |  trans. |    |    +---------+
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |         |    |
+--->             +----->              +----->                 +---------->decoder+--------->clk+->des+------------>         |    |
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |         |    |
   |                |  |                |   |                  |  |    |              |    |           |  |   |    |         |    |
   |                |  |                |   |                  |  |    +--------------+    +-----------+  |   |    +---------+    |
   |                |  |                |   |                  |  |                                       |   |                   |
   +----------------+  +----------------+   +------------------+  +---------------------------------------+   +-------------------+

After reading through ¹, it appears that creating example designs for verilog-ethernet is the first recommended step. This ticket will thereby track progress on this regard, porting verilog-ethernet to KR260. The list below aims to lay out some of the milestones neccessary to achieve the porting goals.

Sources considered

• Source code: https://github.com/alexforencich/verilog-ethernet
• Paper https://cseweb.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf
• Future of corundum https://github.com/corundum/corundum/wiki/Future-of-Corundum
• Corundum overview https://docs.corundum.io/en/latest/modules/overview.html
• Corundum porting guide https://docs.corundum.io/en/latest/porting.html
• Corundum operations, describes reception and transmission operations https://docs.corundum.io/en/latest/operations.html (:warning: useful yet complex to follow)
• K26 SOM XDC file

Related issues and past experiences

• porting to a ZCU102 and ZCU111? #16
• How to implement 1G on the zcu102 SFP connector? #106
• Xilinx Ultrascle+ GTY Reset issue #64

Environment used

• Vitis/Vivado release: 2022.1
• branch of repo used: master

Contributions

• remark license need in reference design example for ZCU102 Add license need to ZCU102 reference design #147
• 10G BASE-R PHY IP reference design example KR260 Add KR260 reference design example #150
• Docker/VSCode devcontainer for simplified reproduction of results Add devcontainer environment for the repo #151

Hardware used

• 1GbE / 10GbE NIC
• SFP+ DAC 10GBASE-CU (2m)
• SFP+ DAC 1GBASE-CU (3m)

Milestones:

• verilog-ethernet in ZCU102 (link to example)
  • inspect source code of 10G BASE-R PHY IP example
  • Understand build system setup and hooks to Vivado
  • Build ethernet-verilog for ZCU102 (10G BASE-R PHY IP core)
  • Test 10G BASE-R PHY
• verilog-ethernet in KR260
  • Port 10G BASE-R PHY example to the SFP+ connector
    • Working at branch https://github.com/vmayoral/verilog-ethernet/tree/kr260
    • K26 SOM XDC file
  • Bring up a 1G PHY example to the SFP+ connector (skipped, focusing instead on the RGMII PHYs)
  • Bring up a 1G MAC example into one of the PL Ethernet PHYs
• Latency performance benchmarking
  • Produce CPU baseline by using Ethernet PHYs connected to the PS and the Linux Networking Stack (LNS)
  • Benchmark 10G BASE-R PHY example to the SFP+ connector
  • Benchmark 1G PHY example to the SFP+ connector (skipped, focusing instead on the RGMII PHYs)
  • Benchmark 1G MAC example into one of the PL Ethernet PHYs

Footnotes

1. Corundum porting guide https://docs.corundum.io/en/latest/porting.html ↩

[vmayoral]

Bumped into a build error while attempting to create IP for ZCU102:

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_sim_netlist.vhdl'. Please regenerate to continue.
# reset_run impl_1
# launch_runs -jobs 4 impl_1
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
eth_xcvr_gt_full_synth_1
eth_xcvr_gt_channel_synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

INFO: [Common 17-206] Exiting Vivado at Mon Feb 13 17:22:56 2023...
make[1]: *** [../common/vivado.mk:115: fpga.runs/impl_1/fpga_routed.dcp] Error 1
make[1]: Leaving directory '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga'
make: *** [Makefile:14: fpga] Error 2

Full prompt of error

victor@accelerationrobotics:~/verilog-ethernet/example/ZCU102/fpga$ make
cd fpga && make
make[1]: Entering directory '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga'
rm -rf defines.v
touch defines.v
for x in ; do echo '`define' $x >> defines.v; done
echo "create_project -force -part xczu9eg-ffvb1156-2-e fpga" > create_project.tcl
echo "add_files -fileset sources_1 defines.v  ../rtl/fpga.v  ../rtl/fpga_core.v  ../rtl/eth_xcvr_phy_wrapper.v  ../rtl/debounce_switch.v  ../rtl/sync_signal.v  ../lib/eth/rtl/eth_mac_10g_fifo.v  ../lib/eth/rtl/eth_mac_10g.v  ../lib/eth/rtl/axis_xgmii_rx_64.v  ../lib/eth/rtl/axis_xgmii_tx_64.v  ../lib/eth/rtl/eth_phy_10g.v  ../lib/eth/rtl/eth_phy_10g_rx.v  ../lib/eth/rtl/eth_phy_10g_rx_if.v  ../lib/eth/rtl/eth_phy_10g_rx_frame_sync.v  ../lib/eth/rtl/eth_phy_10g_rx_ber_mon.v  ../lib/eth/rtl/eth_phy_10g_rx_watchdog.v  ../lib/eth/rtl/eth_phy_10g_tx.v  ../lib/eth/rtl/eth_phy_10g_tx_if.v  ../lib/eth/rtl/xgmii_baser_dec_64.v  ../lib/eth/rtl/xgmii_baser_enc_64.v  ../lib/eth/rtl/lfsr.v  ../lib/eth/rtl/eth_axis_rx.v  ../lib/eth/rtl/eth_axis_tx.v  ../lib/eth/rtl/udp_complete_64.v  ../lib/eth/rtl/udp_checksum_gen_64.v  ../lib/eth/rtl/udp_64.v  ../lib/eth/rtl/udp_ip_rx_64.v  ../lib/eth/rtl/udp_ip_tx_64.v  ../lib/eth/rtl/ip_complete_64.v  ../lib/eth/rtl/ip_64.v  ../lib/eth/rtl/ip_eth_rx_64.v  ../lib/eth/rtl/ip_eth_tx_64.v  ../lib/eth/rtl/ip_arb_mux.v  ../lib/eth/rtl/arp.v  ../lib/eth/rtl/arp_cache.v  ../lib/eth/rtl/arp_eth_rx.v  ../lib/eth/rtl/arp_eth_tx.v  ../lib/eth/rtl/eth_arb_mux.v  ../lib/eth/lib/axis/rtl/arbiter.v  ../lib/eth/lib/axis/rtl/priority_encoder.v  ../lib/eth/lib/axis/rtl/axis_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v  ../lib/eth/lib/axis/rtl/sync_reset.v" >> create_project.tcl
echo "set_property top fpga [current_fileset]" >> create_project.tcl
echo "add_files -fileset constrs_1  ../fpga.xdc  ../lib/eth/syn/vivado/eth_mac_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl" >> create_project.tcl
for x in ; do echo "import_ip $x" >> create_project.tcl; done
for x in  ../ip/eth_xcvr_gt.tcl; do echo "source $x" >> create_project.tcl; done
vivado -nojournal -nolog -mode batch -source create_project.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source create_project.tcl
# create_project -force -part xczu9eg-ffvb1156-2-e fpga
# add_files -fileset sources_1 defines.v  ../rtl/fpga.v  ../rtl/fpga_core.v  ../rtl/eth_xcvr_phy_wrapper.v  ../rtl/debounce_switch.v  ../rtl/sync_signal.v  ../lib/eth/rtl/eth_mac_10g_fifo.v  ../lib/eth/rtl/eth_mac_10g.v  ../lib/eth/rtl/axis_xgmii_rx_64.v  ../lib/eth/rtl/axis_xgmii_tx_64.v  ../lib/eth/rtl/eth_phy_10g.v  ../lib/eth/rtl/eth_phy_10g_rx.v  ../lib/eth/rtl/eth_phy_10g_rx_if.v  ../lib/eth/rtl/eth_phy_10g_rx_frame_sync.v  ../lib/eth/rtl/eth_phy_10g_rx_ber_mon.v  ../lib/eth/rtl/eth_phy_10g_rx_watchdog.v  ../lib/eth/rtl/eth_phy_10g_tx.v  ../lib/eth/rtl/eth_phy_10g_tx_if.v  ../lib/eth/rtl/xgmii_baser_dec_64.v  ../lib/eth/rtl/xgmii_baser_enc_64.v  ../lib/eth/rtl/lfsr.v  ../lib/eth/rtl/eth_axis_rx.v  ../lib/eth/rtl/eth_axis_tx.v  ../lib/eth/rtl/udp_complete_64.v  ../lib/eth/rtl/udp_checksum_gen_64.v  ../lib/eth/rtl/udp_64.v  ../lib/eth/rtl/udp_ip_rx_64.v  ../lib/eth/rtl/udp_ip_tx_64.v  ../lib/eth/rtl/ip_complete_64.v  ../lib/eth/rtl/ip_64.v  ../lib/eth/rtl/ip_eth_rx_64.v  ../lib/eth/rtl/ip_eth_tx_64.v  ../lib/eth/rtl/ip_arb_mux.v  ../lib/eth/rtl/arp.v  ../lib/eth/rtl/arp_cache.v  ../lib/eth/rtl/arp_eth_rx.v  ../lib/eth/rtl/arp_eth_tx.v  ../lib/eth/rtl/eth_arb_mux.v  ../lib/eth/lib/axis/rtl/arbiter.v  ../lib/eth/lib/axis/rtl/priority_encoder.v  ../lib/eth/lib/axis/rtl/axis_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v  ../lib/eth/lib/axis/rtl/sync_reset.v
# set_property top fpga [current_fileset]
# add_files -fileset constrs_1  ../fpga.xdc  ../lib/eth/syn/vivado/eth_mac_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# source ../ip/eth_xcvr_gt.tcl
## set base_name {eth_xcvr_gt}
## set preset {GTH-10GBASE-R}
## set freerun_freq {125}
## set line_rate {10.3125}
## set refclk_freq {156.25}
## set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
## set user_data_width {64}
## set int_data_width {32}
## set extra_ports [list]
## set extra_pll_ports [list {qpll0lock_out}]
## set config [dict create]
## dict set config TX_LINE_RATE $line_rate
## dict set config TX_REFCLK_FREQUENCY $refclk_freq
## dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
## dict set config TX_USER_DATA_WIDTH $user_data_width
## dict set config TX_INT_DATA_WIDTH $int_data_width
## dict set config RX_LINE_RATE $line_rate
## dict set config RX_REFCLK_FREQUENCY $refclk_freq
## dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
## dict set config RX_USER_DATA_WIDTH $user_data_width
## dict set config RX_INT_DATA_WIDTH $int_data_width
## dict set config ENABLE_OPTIONAL_PORTS $extra_ports
## dict set config LOCATE_COMMON {CORE}
## dict set config LOCATE_RESET_CONTROLLER {CORE}
## dict set config LOCATE_TX_USER_CLOCKING {CORE}
## dict set config LOCATE_RX_USER_CLOCKING {CORE}
## dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
## dict set config FREERUN_FREQUENCY $freerun_freq
## dict set config DISABLE_LOC_XDC {1}
## proc create_gtwizard_ip {name preset config} {
##     create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
##     set ip [get_ips $name]
##     set_property CONFIG.preset $preset $ip
##     set config_list {}
##     dict for {name value} $config {
##         lappend config_list "CONFIG.${name}" $value
##     }
##     set_property -dict $config_list $ip
## }
## dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
## dict set config LOCATE_COMMON {CORE}
## create_gtwizard_ip "${base_name}_full" $preset $config
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
create_ip: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2777.340 ; gain = 75.633 ; free physical = 51027 ; free virtual = 63248
## dict set config ENABLE_OPTIONAL_PORTS $extra_ports
## dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
## create_gtwizard_ip "${base_name}_channel" $preset $config
INFO: [Common 17-206] Exiting Vivado at Mon Feb 13 17:22:06 2023...
echo "open_project fpga.xpr" > run_synth.tcl
echo "reset_run synth_1" >> run_synth.tcl
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
echo "wait_on_run synth_1" >> run_synth.tcl
vivado -nojournal -nolog -mode batch -source run_synth.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_synth.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# reset_run synth_1
# launch_runs -jobs 4 synth_1
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'eth_xcvr_gt_full'...
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'eth_xcvr_gt_channel'...
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Mon Feb 13 17:22:29 2023] Launched eth_xcvr_gt_full_synth_1, eth_xcvr_gt_channel_synth_1...
Run output will be captured here:
eth_xcvr_gt_full_synth_1: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/eth_xcvr_gt_full_synth_1/runme.log
eth_xcvr_gt_channel_synth_1: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/eth_xcvr_gt_channel_synth_1/runme.log
[Mon Feb 13 17:22:29 2023] Launched synth_1...
Run output will be captured here: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2766.711 ; gain = 61.035 ; free physical = 50957 ; free virtual = 63201
# wait_on_run synth_1
[Mon Feb 13 17:22:29 2023] Waiting for synth_1 to finish...
[Mon Feb 13 17:22:43 2023] synth_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'eth_xcvr_gt_full_synth_1', 'eth_xcvr_gt_channel_synth_1'
wait_on_runs: Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2766.711 ; gain = 0.000 ; free physical = 50910 ; free virtual = 63156
INFO: [Common 17-206] Exiting Vivado at Mon Feb 13 17:22:43 2023...
echo "open_project fpga.xpr" > run_impl.tcl
echo "reset_run impl_1" >> run_impl.tcl
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
echo "wait_on_run impl_1" >> run_impl.tcl
echo "open_run impl_1" >> run_impl.tcl
echo "report_utilization -file fpga_utilization.rpt" >> run_impl.tcl
echo "report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt" >> run_impl.tcl
vivado -nojournal -nolog -mode batch -source run_impl.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_impl.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_full' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'eth_xcvr_gt_channel' generated file not found '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel_sim_netlist.vhdl'. Please regenerate to continue.
# reset_run impl_1
# launch_runs -jobs 4 impl_1
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
eth_xcvr_gt_full_synth_1
eth_xcvr_gt_channel_synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

INFO: [Common 17-206] Exiting Vivado at Mon Feb 13 17:22:56 2023...
make[1]: *** [../common/vivado.mk:115: fpga.runs/impl_1/fpga_routed.dcp] Error 1
make[1]: Leaving directory '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga'
make: *** [Makefile:14: fpga] Error 2

[vmayoral]

I looked further into the logs as adviced and here's what I found:

victor@accelerationrobotics:~/verilog-ethernet/example/ZCU102/fpga$ du -a| grep log
4	./fpga/fpga.runs/eth_xcvr_gt_full_synth_1/runme.log
4	./fpga/fpga.runs/eth_xcvr_gt_channel_synth_1/runme.log
victor@accelerationrobotics:~/verilog-ethernet/example/ZCU102/fpga$ cat ./fpga/fpga.runs/eth_xcvr_gt_channel_synth_1/runme.log

*** Running vivado
    with args -log eth_xcvr_gt_channel.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source eth_xcvr_gt_channel.tcl


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source eth_xcvr_gt_channel.tcl -notrace
Command: synth_design -top eth_xcvr_gt_channel -part xczu9eg-ffvb1156-2-e -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu9eg'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xczu9eg'. Explanation: The license feature Synthesis could not be found.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
0 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xczu9eg'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". If you are using a license server, verify that the license server is up and running a version of the xilinx daemon that is compatible with the version of Xilinx software that you are using. Note: Vivado 2021.1 and later versions require upgrading your license server tools to the Flex 11.17.2.0 versions. Please confirm with your license admin that the correct version of the license server tools are installed.
INFO: [Common 17-206] Exiting Vivado at Mon Feb 13 20:31:35 2023...

It seems a license issue. Will re-try things once the license is set up appropriately.

[alexforencich]

Ah yep, looks like Vivado needs a license for that part. The Kira SoMs do not require a license, correct?

[vmayoral]

Ah yep, looks like Vivado needs a license for that part. The Kira SoMs do not require a license, correct?

It appears to be the case. Same as with the ZCU102, license is required. For completeness, ZCU102 built successfully after setting up a license:

build prompt

victor@accelerationrobotics:~/verilog-ethernet/example/ZCU102/fpga$ make
cd fpga && make
make[1]: Entering directory '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga'
rm -rf defines.v
touch defines.v
for x in ; do echo '`define' $x >> defines.v; done
echo "create_project -force -part xczu9eg-ffvb1156-2-e fpga" > create_project.tcl
echo "add_files -fileset sources_1 defines.v  ../rtl/fpga.v  ../rtl/fpga_core.v  ../rtl/eth_xcvr_phy_wrapper.v  ../rtl/debounce_switch.v  ../rtl/sync_signal.v  ../lib/eth/rtl/eth_mac_10g_fifo.v  ../lib/eth/rtl/eth_mac_10g.v  ../lib/eth/rtl/axis_xgmii_rx_64.v  ../lib/eth/rtl/axis_xgmii_tx_64.v  ../lib/eth/rtl/eth_phy_10g.v  ../lib/eth/rtl/eth_phy_10g_rx.v  ../lib/eth/rtl/eth_phy_10g_rx_if.v  ../lib/eth/rtl/eth_phy_10g_rx_frame_sync.v  ../lib/eth/rtl/eth_phy_10g_rx_ber_mon.v  ../lib/eth/rtl/eth_phy_10g_rx_watchdog.v  ../lib/eth/rtl/eth_phy_10g_tx.v  ../lib/eth/rtl/eth_phy_10g_tx_if.v  ../lib/eth/rtl/xgmii_baser_dec_64.v  ../lib/eth/rtl/xgmii_baser_enc_64.v  ../lib/eth/rtl/lfsr.v  ../lib/eth/rtl/eth_axis_rx.v  ../lib/eth/rtl/eth_axis_tx.v  ../lib/eth/rtl/udp_complete_64.v  ../lib/eth/rtl/udp_checksum_gen_64.v  ../lib/eth/rtl/udp_64.v  ../lib/eth/rtl/udp_ip_rx_64.v  ../lib/eth/rtl/udp_ip_tx_64.v  ../lib/eth/rtl/ip_complete_64.v  ../lib/eth/rtl/ip_64.v  ../lib/eth/rtl/ip_eth_rx_64.v  ../lib/eth/rtl/ip_eth_tx_64.v  ../lib/eth/rtl/ip_arb_mux.v  ../lib/eth/rtl/arp.v  ../lib/eth/rtl/arp_cache.v  ../lib/eth/rtl/arp_eth_rx.v  ../lib/eth/rtl/arp_eth_tx.v  ../lib/eth/rtl/eth_arb_mux.v  ../lib/eth/lib/axis/rtl/arbiter.v  ../lib/eth/lib/axis/rtl/priority_encoder.v  ../lib/eth/lib/axis/rtl/axis_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v  ../lib/eth/lib/axis/rtl/sync_reset.v" >> create_project.tcl
echo "set_property top fpga [current_fileset]" >> create_project.tcl
echo "add_files -fileset constrs_1  ../fpga.xdc  ../lib/eth/syn/vivado/eth_mac_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl" >> create_project.tcl
for x in ; do echo "import_ip $x" >> create_project.tcl; done
for x in  ../ip/eth_xcvr_gt.tcl; do echo "source $x" >> create_project.tcl; done
vivado -nojournal -nolog -mode batch -source create_project.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source create_project.tcl
# create_project -force -part xczu9eg-ffvb1156-2-e fpga
# add_files -fileset sources_1 defines.v  ../rtl/fpga.v  ../rtl/fpga_core.v  ../rtl/eth_xcvr_phy_wrapper.v  ../rtl/debounce_switch.v  ../rtl/sync_signal.v  ../lib/eth/rtl/eth_mac_10g_fifo.v  ../lib/eth/rtl/eth_mac_10g.v  ../lib/eth/rtl/axis_xgmii_rx_64.v  ../lib/eth/rtl/axis_xgmii_tx_64.v  ../lib/eth/rtl/eth_phy_10g.v  ../lib/eth/rtl/eth_phy_10g_rx.v  ../lib/eth/rtl/eth_phy_10g_rx_if.v  ../lib/eth/rtl/eth_phy_10g_rx_frame_sync.v  ../lib/eth/rtl/eth_phy_10g_rx_ber_mon.v  ../lib/eth/rtl/eth_phy_10g_rx_watchdog.v  ../lib/eth/rtl/eth_phy_10g_tx.v  ../lib/eth/rtl/eth_phy_10g_tx_if.v  ../lib/eth/rtl/xgmii_baser_dec_64.v  ../lib/eth/rtl/xgmii_baser_enc_64.v  ../lib/eth/rtl/lfsr.v  ../lib/eth/rtl/eth_axis_rx.v  ../lib/eth/rtl/eth_axis_tx.v  ../lib/eth/rtl/udp_complete_64.v  ../lib/eth/rtl/udp_checksum_gen_64.v  ../lib/eth/rtl/udp_64.v  ../lib/eth/rtl/udp_ip_rx_64.v  ../lib/eth/rtl/udp_ip_tx_64.v  ../lib/eth/rtl/ip_complete_64.v  ../lib/eth/rtl/ip_64.v  ../lib/eth/rtl/ip_eth_rx_64.v  ../lib/eth/rtl/ip_eth_tx_64.v  ../lib/eth/rtl/ip_arb_mux.v  ../lib/eth/rtl/arp.v  ../lib/eth/rtl/arp_cache.v  ../lib/eth/rtl/arp_eth_rx.v  ../lib/eth/rtl/arp_eth_tx.v  ../lib/eth/rtl/eth_arb_mux.v  ../lib/eth/lib/axis/rtl/arbiter.v  ../lib/eth/lib/axis/rtl/priority_encoder.v  ../lib/eth/lib/axis/rtl/axis_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo.v  ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v  ../lib/eth/lib/axis/rtl/sync_reset.v
# set_property top fpga [current_fileset]
# add_files -fileset constrs_1  ../fpga.xdc  ../lib/eth/syn/vivado/eth_mac_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl  ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl
# source ../ip/eth_xcvr_gt.tcl
## set base_name {eth_xcvr_gt}
## set preset {GTH-10GBASE-R}
## set freerun_freq {125}
## set line_rate {10.3125}
## set refclk_freq {156.25}
## set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
## set user_data_width {64}
## set int_data_width {32}
## set extra_ports [list]
## set extra_pll_ports [list {qpll0lock_out}]
## set config [dict create]
## dict set config TX_LINE_RATE $line_rate
## dict set config TX_REFCLK_FREQUENCY $refclk_freq
## dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
## dict set config TX_USER_DATA_WIDTH $user_data_width
## dict set config TX_INT_DATA_WIDTH $int_data_width
## dict set config RX_LINE_RATE $line_rate
## dict set config RX_REFCLK_FREQUENCY $refclk_freq
## dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
## dict set config RX_USER_DATA_WIDTH $user_data_width
## dict set config RX_INT_DATA_WIDTH $int_data_width
## dict set config ENABLE_OPTIONAL_PORTS $extra_ports
## dict set config LOCATE_COMMON {CORE}
## dict set config LOCATE_RESET_CONTROLLER {CORE}
## dict set config LOCATE_TX_USER_CLOCKING {CORE}
## dict set config LOCATE_RX_USER_CLOCKING {CORE}
## dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
## dict set config FREERUN_FREQUENCY $freerun_freq
## dict set config DISABLE_LOC_XDC {1}
## proc create_gtwizard_ip {name preset config} {
##     create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
##     set ip [get_ips $name]
##     set_property CONFIG.preset $preset $ip
##     set config_list {}
##     dict for {name value} $config {
##         lappend config_list "CONFIG.${name}" $value
##     }
##     set_property -dict $config_list $ip
## }
## dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
## dict set config LOCATE_COMMON {CORE}
## create_gtwizard_ip "${base_name}_full" $preset $config
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
create_ip: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2777.309 ; gain = 71.633 ; free physical = 50364 ; free virtual = 63144
## dict set config ENABLE_OPTIONAL_PORTS $extra_ports
## dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
## create_gtwizard_ip "${base_name}_channel" $preset $config
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:09:42 2023...
echo "open_project fpga.xpr" > run_synth.tcl
echo "reset_run synth_1" >> run_synth.tcl
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
echo "wait_on_run synth_1" >> run_synth.tcl
vivado -nojournal -nolog -mode batch -source run_synth.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_synth.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# reset_run synth_1
# launch_runs -jobs 4 synth_1
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'eth_xcvr_gt_full'...
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'eth_xcvr_gt_channel'...
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Tue Feb 14 09:10:04 2023] Launched eth_xcvr_gt_full_synth_1, eth_xcvr_gt_channel_synth_1...
Run output will be captured here:
eth_xcvr_gt_full_synth_1: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/eth_xcvr_gt_full_synth_1/runme.log
eth_xcvr_gt_channel_synth_1: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/eth_xcvr_gt_channel_synth_1/runme.log
[Tue Feb 14 09:10:04 2023] Launched synth_1...
Run output will be captured here: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2766.707 ; gain = 61.035 ; free physical = 50355 ; free virtual = 63139
# wait_on_run synth_1
[Tue Feb 14 09:10:04 2023] Waiting for synth_1 to finish...

*** Running vivado
    with args -log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source fpga.tcl -notrace
Command: synth_design -top fpga -part xczu9eg-ffvb1156-2-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 59525
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:89]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:91]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:93]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:85]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:87]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:89]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:125]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:127]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:131]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:132]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:135]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:136]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:138]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:140]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:141]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:121]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:123]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_xgmii_tx_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:90]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_xgmii_tx_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:91]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_arb_mux' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:90]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_rx.v:80]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_rx.v:82]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_rx.v:84]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_tx.v:79]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_tx.v:81]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_tx.v:83]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_mac_10g_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:138]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_ber_mon' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:62]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_frame_sync' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:56]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_frame_sync' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:57]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_watchdog' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:71]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'ip_arb_mux' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:116]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'lfsr' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:355]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'priority_encoder' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:47]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'priority_encoder' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:48]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'udp_checksum_gen_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_checksum_gen_64.v:145]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2923.473 ; gain = 209.797 ; free physical = 47658 ; free virtual = 60506
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'fpga' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga.v:34]
INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55701]
	Parameter DIFF_TERM bound to: FALSE - type: string
	Parameter IBUF_LOW_PWR bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55701]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:1082]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:1082]
INFO: [Synth 8-6157] synthesizing module 'MMCME4_BASE' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:64029]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string
	Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
	Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
	Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
	Parameter REF_JITTER1 bound to: 0.010000 - type: double
	Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME4_BASE' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:64029]
INFO: [Synth 8-6157] synthesizing module 'sync_reset' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
	Parameter N bound to: 4 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sync_reset' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
INFO: [Synth 8-6157] synthesizing module 'debounce_switch' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/debounce_switch.v:34]
	Parameter WIDTH bound to: 9 - type: integer
	Parameter N bound to: 8 - type: integer
	Parameter RATE bound to: 156000 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'debounce_switch' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/debounce_switch.v:34]
WARNING: [Synth 8-689] width (13) of port connection 'in' does not match port width (9) of module 'debounce_switch' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga.v:212]
WARNING: [Synth 8-689] width (13) of port connection 'out' does not match port width (9) of module 'debounce_switch' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga.v:218]
INFO: [Synth 8-6157] synthesizing module 'sync_signal' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/sync_signal.v:35]
	Parameter WIDTH bound to: 2 - type: integer
	Parameter N bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sync_signal' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/sync_signal.v:35]
INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE4' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55395]
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE4' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55395]
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_phy_wrapper' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
	Parameter HAS_COMMON bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_gt_full' [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-59518-accelerationrobotics/realtime/eth_xcvr_gt_full_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_gt_full' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-59518-accelerationrobotics/realtime/eth_xcvr_gt_full_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BIT_REVERSE bound to: 1 - type: integer
	Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
	Parameter PRBS31_ENABLE bound to: 0 - type: integer
	Parameter TX_SERDES_PIPELINE bound to: 0 - type: integer
	Parameter RX_SERDES_PIPELINE bound to: 0 - type: integer
	Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
	Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
	Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BIT_REVERSE bound to: 1 - type: integer
	Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
	Parameter PRBS31_ENABLE bound to: 0 - type: integer
	Parameter SERDES_PIPELINE bound to: 0 - type: integer
	Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
	Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
	Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_if' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BIT_REVERSE bound to: 1 - type: integer
	Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
	Parameter PRBS31_ENABLE bound to: 0 - type: integer
	Parameter SERDES_PIPELINE bound to: 0 - type: integer
	Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
	Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
	Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 58 - type: integer
	Parameter LFSR_POLY bound to: 58'b0000000000000000001000000000000000000000000000000000000001
	Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
	Parameter LFSR_FEED_FORWARD bound to: 1 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized0' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 31 - type: integer
	Parameter LFSR_POLY bound to: 31'b0010000000000000000000000000001
	Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
	Parameter LFSR_FEED_FORWARD bound to: 1 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 66 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_frame_sync' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:34]
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
	Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_frame_sync' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_ber_mon' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:34]
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_ber_mon' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_watchdog' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:34]
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_watchdog' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_if' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v:34]
INFO: [Synth 8-6157] synthesizing module 'xgmii_baser_dec_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/xgmii_baser_dec_64.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xgmii_baser_dec_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/xgmii_baser_dec_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_tx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_tx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BIT_REVERSE bound to: 1 - type: integer
	Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
	Parameter PRBS31_ENABLE bound to: 0 - type: integer
	Parameter SERDES_PIPELINE bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xgmii_baser_enc_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/xgmii_baser_enc_64.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xgmii_baser_enc_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/xgmii_baser_enc_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_tx_if' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter HDR_WIDTH bound to: 2 - type: integer
	Parameter BIT_REVERSE bound to: 1 - type: integer
	Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
	Parameter PRBS31_ENABLE bound to: 0 - type: integer
	Parameter SERDES_PIPELINE bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized1' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 58 - type: integer
	Parameter LFSR_POLY bound to: 58'b0000000000000000001000000000000000000000000000000000000001
	Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized1' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized2' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 31 - type: integer
	Parameter LFSR_POLY bound to: 31'b0010000000000000000000000000001
	Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 66 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized2' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_tx_if' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_tx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g_tx.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_phy_10g.v:34]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_tx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:282]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_rx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:284]
WARNING: [Synth 8-7071] port 'rx_status' of module 'eth_phy_10g' is unconnected for instance 'phy_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
WARNING: [Synth 8-7023] instance 'phy_inst' of module 'eth_phy_10g' has 23 connections declared, but only 22 given [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_phy_wrapper' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_phy_wrapper__parameterized0' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
	Parameter HAS_COMMON bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_gt_channel' [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-59518-accelerationrobotics/realtime/eth_xcvr_gt_channel_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_gt_channel' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-59518-accelerationrobotics/realtime/eth_xcvr_gt_channel_stub.v:5]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_tx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:282]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_rx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:284]
WARNING: [Synth 8-7071] port 'rx_status' of module 'eth_phy_10g' is unconnected for instance 'phy_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
WARNING: [Synth 8-7023] instance 'phy_inst' of module 'eth_phy_10g' has 23 connections declared, but only 22 given [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_phy_wrapper__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
INFO: [Synth 8-6157] synthesizing module 'fpga_core' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_mac_10g_fifo' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:34]
	Parameter ENABLE_PADDING bound to: 1 - type: integer
	Parameter ENABLE_DIC bound to: 1 - type: integer
	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
	Parameter TX_FIFO_DEPTH bound to: 4096 - type: integer
	Parameter TX_FRAME_FIFO bound to: 1 - type: integer
	Parameter RX_FIFO_DEPTH bound to: 4096 - type: integer
	Parameter RX_FRAME_FIFO bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_mac_10g' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter ENABLE_PADDING bound to: 1 - type: integer
	Parameter ENABLE_DIC bound to: 1 - type: integer
	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
	Parameter PTP_PERIOD_NS bound to: 4'b0110
	Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
	Parameter TX_PTP_TS_ENABLE bound to: 0 - type: integer
	Parameter TX_PTP_TS_WIDTH bound to: 96 - type: integer
	Parameter TX_PTP_TAG_ENABLE bound to: 0 - type: integer
	Parameter TX_PTP_TAG_WIDTH bound to: 16 - type: integer
	Parameter RX_PTP_TS_ENABLE bound to: 0 - type: integer
	Parameter RX_PTP_TS_WIDTH bound to: 96 - type: integer
	Parameter TX_USER_WIDTH bound to: 1 - type: integer
	Parameter RX_USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_xgmii_rx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter PTP_PERIOD_NS bound to: 4'b0110
	Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
	Parameter PTP_TS_ENABLE bound to: 0 - type: integer
	Parameter PTP_TS_WIDTH bound to: 96 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized3' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized3' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-226] default block is never used [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:207]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:268]
INFO: [Synth 8-6155] done synthesizing module 'axis_xgmii_rx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_xgmii_tx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter CTRL_WIDTH bound to: 8 - type: integer
	Parameter ENABLE_PADDING bound to: 1 - type: integer
	Parameter ENABLE_DIC bound to: 1 - type: integer
	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
	Parameter PTP_PERIOD_NS bound to: 4'b0110
	Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
	Parameter PTP_TS_ENABLE bound to: 0 - type: integer
	Parameter PTP_TS_WIDTH bound to: 96 - type: integer
	Parameter PTP_TAG_ENABLE bound to: 0 - type: integer
	Parameter PTP_TAG_WIDTH bound to: 16 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized4' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 8 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized4' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized5' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 16 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized5' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized6' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 24 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized6' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized7' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 32 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized7' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized8' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 40 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized8' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized9' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 48 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized9' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized10' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
	Parameter LFSR_WIDTH bound to: 32 - type: integer
	Parameter LFSR_POLY bound to: 79764919 - type: integer
	Parameter LFSR_CONFIG bound to: GALOIS - type: string
	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
	Parameter REVERSE bound to: 1 - type: integer
	Parameter DATA_WIDTH bound to: 56 - type: integer
	Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized10' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:332]
INFO: [Synth 8-6155] done synthesizing module 'axis_xgmii_tx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_mac_10g' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g.v:34]
WARNING: [Synth 8-7071] port 'tx_start_packet' of module 'eth_mac_10g' is unconnected for instance 'eth_mac_10g_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
WARNING: [Synth 8-7071] port 'rx_start_packet' of module 'eth_mac_10g' is unconnected for instance 'eth_mac_10g_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
WARNING: [Synth 8-7023] instance 'eth_mac_10g_inst' of module 'eth_mac_10g' has 30 connections declared, but only 28 given [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
	Parameter DEPTH bound to: 4096 - type: integer
	Parameter S_DATA_WIDTH bound to: 64 - type: integer
	Parameter S_KEEP_ENABLE bound to: 1'b1
	Parameter S_KEEP_WIDTH bound to: 8 - type: integer
	Parameter M_DATA_WIDTH bound to: 64 - type: integer
	Parameter M_KEEP_ENABLE bound to: 1 - type: integer
	Parameter M_KEEP_WIDTH bound to: 8 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter RAM_PIPELINE bound to: 1 - type: integer
	Parameter FRAME_FIFO bound to: 1 - type: integer
	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
	Parameter USER_BAD_FRAME_MASK bound to: 1'b1
	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
	Parameter DROP_BAD_FRAME bound to: 1 - type: integer
	Parameter DROP_WHEN_FULL bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
	Parameter DEPTH bound to: 4096 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter LAST_ENABLE bound to: 1 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter ID_WIDTH bound to: 8 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter DEST_WIDTH bound to: 8 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter RAM_PIPELINE bound to: 1 - type: integer
	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer
	Parameter FRAME_FIFO bound to: 1 - type: integer
	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
	Parameter USER_BAD_FRAME_MASK bound to: 1'b1
	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
	Parameter DROP_BAD_FRAME bound to: 1 - type: integer
	Parameter DROP_WHEN_FULL bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter__parameterized0' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
	Parameter DEPTH bound to: 4096 - type: integer
	Parameter S_DATA_WIDTH bound to: 64 - type: integer
	Parameter S_KEEP_ENABLE bound to: 1 - type: integer
	Parameter S_KEEP_WIDTH bound to: 8 - type: integer
	Parameter M_DATA_WIDTH bound to: 64 - type: integer
	Parameter M_KEEP_ENABLE bound to: 1'b1
	Parameter M_KEEP_WIDTH bound to: 8 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter RAM_PIPELINE bound to: 1 - type: integer
	Parameter FRAME_FIFO bound to: 1 - type: integer
	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
	Parameter USER_BAD_FRAME_MASK bound to: 1'b1
	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
	Parameter DROP_BAD_FRAME bound to: 1 - type: integer
	Parameter DROP_WHEN_FULL bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo__parameterized0' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
	Parameter DEPTH bound to: 4096 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter LAST_ENABLE bound to: 1 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter ID_WIDTH bound to: 8 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter DEST_WIDTH bound to: 8 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter RAM_PIPELINE bound to: 1 - type: integer
	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer
	Parameter FRAME_FIFO bound to: 1 - type: integer
	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
	Parameter USER_BAD_FRAME_MASK bound to: 1'b1
	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
	Parameter DROP_BAD_FRAME bound to: 1 - type: integer
	Parameter DROP_WHEN_FULL bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_mac_10g_fifo' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:34]
WARNING: [Synth 8-7071] port 'ptp_sample_clk' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_96' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_tag' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_valid' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_ready' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'tx_error_underflow' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'ptp_ts_96' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7071] port 'ptp_ts_step' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
WARNING: [Synth 8-7023] instance 'eth_mac_10g_fifo_inst' of module 'eth_mac_10g_fifo' has 39 connections declared, but only 31 given [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:351]
INFO: [Synth 8-6157] synthesizing module 'eth_axis_rx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_rx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_axis_rx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_axis_tx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_tx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_axis_tx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_axis_tx.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_complete_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_arb_mux' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:34]
	Parameter S_COUNT bound to: 2 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'arbiter' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
	Parameter PORTS bound to: 2 - type: integer
	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
	Parameter ARB_BLOCK bound to: 1 - type: integer
	Parameter ARB_BLOCK_ACK bound to: 1 - type: integer
	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'priority_encoder' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
	Parameter WIDTH bound to: 2 - type: integer
	Parameter LSB_HIGH_PRIORITY bound to: 1 - type: integer
WARNING: [Synth 8-693] zero replication count - replication ignored [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:51]
INFO: [Synth 8-6155] done synthesizing module 'priority_encoder' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
INFO: [Synth 8-6155] done synthesizing module 'arbiter' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
INFO: [Synth 8-6155] done synthesizing module 'ip_arb_mux' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_complete_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_complete_64.v:34]
	Parameter ARP_CACHE_ADDR_WIDTH bound to: 9 - type: integer
	Parameter ARP_REQUEST_RETRY_COUNT bound to: 4 - type: integer
	Parameter ARP_REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer
	Parameter ARP_REQUEST_TIMEOUT bound to: -544967296 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_arb_mux' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:34]
	Parameter S_COUNT bound to: 2 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_arb_mux' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_eth_rx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_rx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_rx_64.v:345]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_rx_64.v:247]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_rx_64.v:317]
INFO: [Synth 8-6155] done synthesizing module 'ip_eth_rx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_eth_tx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_tx_64.v:324]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_tx_64.v:215]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_tx_64.v:278]
INFO: [Synth 8-6155] done synthesizing module 'ip_eth_tx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_eth_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_64.v:282]
INFO: [Synth 8-6155] done synthesizing module 'ip_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer
	Parameter REQUEST_RETRY_COUNT bound to: 4 - type: integer
	Parameter REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer
	Parameter REQUEST_TIMEOUT bound to: -544967296 - type: integer
INFO: [Synth 8-6157] synthesizing module 'arp_eth_rx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_eth_rx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp_eth_tx' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:34]
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_eth_tx' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp_cache' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_cache.v:34]
	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_cache' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_cache.v:34]
INFO: [Synth 8-6155] done synthesizing module 'arp' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp.v:34]
INFO: [Synth 8-6155] done synthesizing module 'ip_complete_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_64.v:34]
	Parameter CHECKSUM_GEN_ENABLE bound to: 1 - type: integer
	Parameter CHECKSUM_PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer
	Parameter CHECKSUM_HEADER_FIFO_DEPTH bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'udp_checksum_gen_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_checksum_gen_64.v:34]
	Parameter PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer
	Parameter HEADER_FIFO_DEPTH bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_fifo' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
	Parameter DEPTH bound to: 2048 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter LAST_ENABLE bound to: 1 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter FRAME_FIFO bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_fifo' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_checksum_gen_64.v:462]
INFO: [Synth 8-6155] done synthesizing module 'udp_checksum_gen_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_checksum_gen_64.v:34]
WARNING: [Synth 8-7071] port 'm_ip_protocol' of module 'udp_checksum_gen_64' is unconnected for instance 'udp_checksum_gen_64_inst' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_64.v:271]
WARNING: [Synth 8-7023] instance 'udp_checksum_gen_64_inst' of module 'udp_checksum_gen_64' has 55 connections declared, but only 54 given [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_64.v:271]
INFO: [Synth 8-6157] synthesizing module 'udp_ip_rx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_rx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_rx_64.v:247]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_rx_64.v:284]
INFO: [Synth 8-6155] done synthesizing module 'udp_ip_rx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_ip_tx_64' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_tx_64.v:238]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_tx_64.v:273]
INFO: [Synth 8-6155] done synthesizing module 'udp_ip_tx_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_ip_tx_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'udp_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'udp_complete_64' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_fifo__parameterized0' [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
	Parameter DEPTH bound to: 8192 - type: integer
	Parameter DATA_WIDTH bound to: 64 - type: integer
	Parameter KEEP_ENABLE bound to: 1 - type: integer
	Parameter KEEP_WIDTH bound to: 8 - type: integer
	Parameter ID_ENABLE bound to: 0 - type: integer
	Parameter DEST_ENABLE bound to: 0 - type: integer
	Parameter USER_ENABLE bound to: 1 - type: integer
	Parameter USER_WIDTH bound to: 1 - type: integer
	Parameter FRAME_FIFO bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_fifo__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'fpga_core' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:34]
INFO: [Synth 8-6155] done synthesizing module 'fpga' (0#1) [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga.v:34]
WARNING: [Synth 8-3848] Net xcvr_qpll0reset_out in module/entity eth_xcvr_phy_wrapper does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:68]
WARNING: [Synth 8-3848] Net xcvr_qpll0lock_out in module/entity eth_xcvr_phy_wrapper__parameterized0 does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:60]
WARNING: [Synth 8-3848] Net xcvr_qpll0outclk_out in module/entity eth_xcvr_phy_wrapper__parameterized0 does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:61]
WARNING: [Synth 8-3848] Net xcvr_qpll0outrefclk_out in module/entity eth_xcvr_phy_wrapper__parameterized0 does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v:62]
WARNING: [Synth 8-6014] Unused sequential element ptp_ts_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:428]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:603]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_adj_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:604]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_tag_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:605]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:606]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_int_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:607]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_borrow_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:608]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:373]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:386]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_gray_sync2_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:484]
WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:565]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:373]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:386]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_gray_sync2_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:484]
WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:565]
WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tid_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:376]
WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tdest_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:377]
WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tid_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:383]
WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tdest_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/ip_arb_mux.v:384]
WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tid_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:285]
WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tdest_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:286]
WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tid_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:292]
WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tdest_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/eth_arb_mux.v:293]
WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_rx.v:172]
WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/arp_eth_tx.v:161]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_cur_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:174]
WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:268]
WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:213]
WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:214]
WARNING: [Synth 8-6014] Unused sequential element s_udp_payload_axis_tready_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/rtl/udp_checksum_gen_64.v:555]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_cur_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:174]
WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:268]
WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:213]
WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:214]
WARNING: [Synth 8-3848] Net uart_txd in module/entity fpga_core does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:58]
WARNING: [Synth 8-3848] Net uart_cts in module/entity fpga_core does not have driver. [/home/victor/verilog-ethernet/example/ZCU102/fpga/rtl/fpga_core.v:60]
WARNING: [Synth 8-3917] design fpga has port sfp0_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp1_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp2_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp3_tx_disable_b driven by constant 1
WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[15] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[14] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[13] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[12] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[11] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[10] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[9] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[8] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[7] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[6] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[5] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[4] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[3] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[2] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[1] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[0] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[15] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[14] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[13] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[12] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[11] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[10] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[9] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[8] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[7] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[6] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[5] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[4] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[3] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[2] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[1] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[0] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[31] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[30] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[29] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[28] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[27] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[26] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[25] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[24] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[23] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[22] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[21] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[20] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[19] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[18] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[17] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[16] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[15] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[14] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[13] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[12] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[11] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[10] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[9] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[8] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[7] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[6] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[5] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[4] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[3] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[2] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[1] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[0] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[15] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[14] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[13] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[12] in module eth_arb_mux is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:05:12 ; elapsed = 00:05:14 . Memory (MB): peak = 6201.613 ; gain = 3487.938 ; free physical = 47358 ; free virtual = 60198
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:05:13 ; elapsed = 00:05:15 . Memory (MB): peak = 6201.613 ; gain = 3487.938 ; free physical = 47358 ; free virtual = 60198
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:05:13 ; elapsed = 00:05:15 . Memory (MB): peak = 6201.613 ; gain = 3487.938 ; free physical = 47358 ; free virtual = 60198
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 6201.613 ; gain = 0.000 ; free physical = 47351 ; free virtual = 60191
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full/eth_xcvr_gt_full_in_context.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full/eth_xcvr_gt_full_in_context.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp1_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp1_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp2_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp2_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp3_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel/eth_xcvr_gt_channel_in_context.xdc] for cell 'sfp3_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_10g_fifo_inst
INFO: [Timing 38-2] Deriving generated clocks [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
Inserting timing constraints for sync_reset instance sync_reset_125mhz_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/tx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp1_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp1_phy_inst/tx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp2_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp2_phy_inst/tx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp3_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp3_phy_inst/tx_reset_sync_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6320.449 ; gain = 0.000 ; free physical = 47297 ; free virtual = 60138
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 4 instances were transformed.
  BUFG => BUFGCE: 2 instances
  IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
  MMCME4_BASE => MMCME4_ADV: 1 instance

Constraint Validation Runtime : Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6320.449 ; gain = 0.000 ; free physical = 47297 ; free virtual = 60138
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:05:25 ; elapsed = 00:05:27 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 47763 ; free virtual = 60603
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "arp_cache:/valid_mem_reg" of size (depth=512 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding
---------------------------------------------------------------------------------------------------
              STATE_IDLE |                             0001 |                              000
       STATE_READ_HEADER |                             0010 |                              001
      STATE_READ_PAYLOAD |                             0100 |                              010
 STATE_READ_PAYLOAD_LAST |                             1000 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'udp_ip_rx_64'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding
---------------------------------------------------------------------------------------------------
              STATE_IDLE |                               00 |                              000
      STATE_WRITE_HEADER |                               01 |                              001
     STATE_WRITE_PAYLOAD |                               10 |                              010
STATE_WRITE_PAYLOAD_LAST |                               11 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_tx_64'
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "axis_fifo__parameterized0:/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "axis_fifo__parameterized0:/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 2 for RAM "axis_fifo__parameterized0:/mem_reg"
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:05:34 ; elapsed = 00:05:36 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 45488 ; free virtual = 58333
---------------------------------------------------------------------------------
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
	   2 Input   36 Bit       Adders := 1
	   2 Input   32 Bit       Adders := 2
	   3 Input   32 Bit       Adders := 1
	   3 Input   20 Bit       Adders := 1
	   9 Input   20 Bit       Adders := 1
	   3 Input   18 Bit       Adders := 1
	   2 Input   18 Bit       Adders := 2
	   2 Input   17 Bit       Adders := 7
	   4 Input   17 Bit       Adders := 2
	   2 Input   16 Bit       Adders := 12
	   2 Input   15 Bit       Adders := 8
	   2 Input   11 Bit       Adders := 3
	   2 Input   10 Bit       Adders := 10
	   2 Input    9 Bit       Adders := 4
	   2 Input    8 Bit       Adders := 1
	   5 Input    8 Bit       Adders := 1
	   2 Input    6 Bit       Adders := 8
	   2 Input    4 Bit       Adders := 18
	   2 Input    3 Bit       Adders := 5
	   2 Input    2 Bit       Adders := 2
	   2 Input    1 Bit       Adders := 2
+---XORs :
	   2 Input     32 Bit         XORs := 1
	   2 Input     11 Bit         XORs := 1
	   2 Input     10 Bit         XORs := 10
	   2 Input      9 Bit         XORs := 1
	   2 Input      2 Bit         XORs := 1
	   2 Input      1 Bit         XORs := 1097
	   4 Input      1 Bit         XORs := 202
	   5 Input      1 Bit         XORs := 94
	   6 Input      1 Bit         XORs := 81
	   3 Input      1 Bit         XORs := 769
	  10 Input      1 Bit         XORs := 26
	   9 Input      1 Bit         XORs := 33
	   7 Input      1 Bit         XORs := 50
	   8 Input      1 Bit         XORs := 44
	  11 Input      1 Bit         XORs := 25
	  12 Input      1 Bit         XORs := 23
	  17 Input      1 Bit         XORs := 39
	  18 Input      1 Bit         XORs := 33
	  16 Input      1 Bit         XORs := 34
	  20 Input      1 Bit         XORs := 29
	  19 Input      1 Bit         XORs := 25
	  21 Input      1 Bit         XORs := 21
	  15 Input      1 Bit         XORs := 31
	  24 Input      1 Bit         XORs := 24
	  26 Input      1 Bit         XORs := 16
	  25 Input      1 Bit         XORs := 12
	  22 Input      1 Bit         XORs := 26
	  27 Input      1 Bit         XORs := 12
	  28 Input      1 Bit         XORs := 14
	  29 Input      1 Bit         XORs := 4
	  35 Input      1 Bit         XORs := 4
	  30 Input      1 Bit         XORs := 3
	  34 Input      1 Bit         XORs := 2
	  33 Input      1 Bit         XORs := 2
	  23 Input      1 Bit         XORs := 11
	  32 Input      1 Bit         XORs := 7
	  31 Input      1 Bit         XORs := 4
	  43 Input      1 Bit         XORs := 2
	  37 Input      1 Bit         XORs := 2
	  13 Input      1 Bit         XORs := 11
	  14 Input      1 Bit         XORs := 13
+---Registers :
	               74 Bit    Registers := 8
	               64 Bit    Registers := 47
	               58 Bit    Registers := 8
	               48 Bit    Registers := 32
	               36 Bit    Registers := 1
	               32 Bit    Registers := 24
	               24 Bit    Registers := 1
	               20 Bit    Registers := 2
	               17 Bit    Registers := 4
	               16 Bit    Registers := 50
	               15 Bit    Registers := 8
	               13 Bit    Registers := 6
	               11 Bit    Registers := 2
	               10 Bit    Registers := 22
	                9 Bit    Registers := 5
	                8 Bit    Registers := 60
	                6 Bit    Registers := 14
	                4 Bit    Registers := 41
	                3 Bit    Registers := 12
	                2 Bit    Registers := 38
	                1 Bit    Registers := 287
+---RAMs :
	              74K Bit	(1024 X 74 bit)          RAMs := 1
	              37K Bit	(512 X 74 bit)          RAMs := 2
	              24K Bit	(512 X 48 bit)          RAMs := 1
	              18K Bit	(256 X 74 bit)          RAMs := 1
	              16K Bit	(512 X 32 bit)          RAMs := 1
	              512 Bit	(512 X 1 bit)          RAMs := 1
	              384 Bit	(8 X 48 bit)          RAMs := 2
	              256 Bit	(8 X 32 bit)          RAMs := 2
	              128 Bit	(8 X 16 bit)          RAMs := 7
	              104 Bit	(8 X 13 bit)          RAMs := 1
	               64 Bit	(8 X 8 bit)          RAMs := 1
	               48 Bit	(8 X 6 bit)          RAMs := 1
	               32 Bit	(8 X 4 bit)          RAMs := 2
	               24 Bit	(8 X 3 bit)          RAMs := 1
	               16 Bit	(8 X 2 bit)          RAMs := 1
+---Muxes :
	   2 Input   64 Bit        Muxes := 88
	   3 Input   64 Bit        Muxes := 6
	   7 Input   64 Bit        Muxes := 2
	   5 Input   64 Bit        Muxes := 1
	   6 Input   64 Bit        Muxes := 1
	   4 Input   64 Bit        Muxes := 2
	  16 Input   64 Bit        Muxes := 4
	   2 Input   48 Bit        Muxes := 21
	   6 Input   36 Bit        Muxes := 1
	   3 Input   36 Bit        Muxes := 1
	   2 Input   36 Bit        Muxes := 1
	   2 Input   32 Bit        Muxes := 15
	   8 Input   32 Bit        Muxes := 1
	   6 Input   32 Bit        Muxes := 1
	   5 Input   28 Bit        Muxes := 1
	   5 Input   20 Bit        Muxes := 1
	   2 Input   18 Bit        Muxes := 1
	   6 Input   17 Bit        Muxes := 2
	   2 Input   16 Bit        Muxes := 15
	   5 Input   16 Bit        Muxes := 1
	   6 Input   16 Bit        Muxes := 2
	   4 Input   16 Bit        Muxes := 2
	   2 Input   15 Bit        Muxes := 4
	   2 Input   13 Bit        Muxes := 1
	   2 Input   10 Bit        Muxes := 24
	   2 Input    9 Bit        Muxes := 1
	   2 Input    8 Bit        Muxes := 87
	   9 Input    8 Bit        Muxes := 2
	   3 Input    8 Bit        Muxes := 7
	   8 Input    8 Bit        Muxes := 2
	   7 Input    8 Bit        Muxes := 2
	   5 Input    8 Bit        Muxes := 5
	   4 Input    8 Bit        Muxes := 7
	   6 Input    8 Bit        Muxes := 1
	  11 Input    8 Bit        Muxes := 1
	  10 Input    8 Bit        Muxes := 32
	  16 Input    8 Bit        Muxes := 4
	  11 Input    7 Bit        Muxes := 32
	   7 Input    6 Bit        Muxes := 1
	   2 Input    6 Bit        Muxes := 17
	   5 Input    6 Bit        Muxes := 1
	   6 Input    6 Bit        Muxes := 2
	   2 Input    4 Bit        Muxes := 20
	   8 Input    4 Bit        Muxes := 1
	   9 Input    4 Bit        Muxes := 5
	   3 Input    4 Bit        Muxes := 1
	   4 Input    4 Bit        Muxes := 5
	  16 Input    4 Bit        Muxes := 4
	   9 Input    3 Bit        Muxes := 1
	   2 Input    3 Bit        Muxes := 34
	   7 Input    3 Bit        Muxes := 1
	  21 Input    3 Bit        Muxes := 1
	   4 Input    3 Bit        Muxes := 3
	   3 Input    3 Bit        Muxes := 9
	   5 Input    3 Bit        Muxes := 1
	  28 Input    3 Bit        Muxes := 1
	   6 Input    3 Bit        Muxes := 4
	   3 Input    2 Bit        Muxes := 9
	   2 Input    2 Bit        Muxes := 58
	   7 Input    2 Bit        Muxes := 1
	   4 Input    2 Bit        Muxes := 2
	   2 Input    1 Bit        Muxes := 516
	   3 Input    1 Bit        Muxes := 16
	   7 Input    1 Bit        Muxes := 10
	   4 Input    1 Bit        Muxes := 33
	   5 Input    1 Bit        Muxes := 22
	   6 Input    1 Bit        Muxes := 20
	  10 Input    1 Bit        Muxes := 32
	  16 Input    1 Bit        Muxes := 8
	  18 Input    1 Bit        Muxes := 4
	  11 Input    1 Bit        Muxes := 32
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 2520 (col length:168)
BRAMs: 1824 (col length: RAMB18 168 RAMB36 84)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst/valid_mem_reg" of size (depth=512 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3917] design fpga has port sfp0_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp1_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp2_tx_disable_b driven by constant 1
WARNING: [Synth 8-3917] design fpga has port sfp3_tx_disable_b driven by constant 1
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst/valid_mem_reg" of size (depth=512 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "core_inst/udp_payload_fifo/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "core_inst/udp_payload_fifo/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 2 for RAM "core_inst/udp_payload_fifo/mem_reg"
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:06:07 ; elapsed = 00:06:25 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41659 ; free virtual = 54529
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name                                                               | RTL Object                                    | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|core_inst/eth_mac_10g_fifo_inst                                           | tx_fifo/fifo_inst/mem_reg                     | 512 x 74(NO_CHANGE)    | W |   | 512 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/eth_mac_10g_fifo_inst                                           | rx_fifo/fifo_inst/mem_reg                     | 512 x 74(NO_CHANGE)    | W |   | 512 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | ip_addr_mem_reg                               | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      |                 |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | mac_addr_mem_reg                              | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      |                 |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/payload_fifo/mem_reg | 256 x 74(READ_FIRST)   | W |   | 256 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/udp_payload_fifo                                                | mem_reg                                       | 1 K x 74(READ_FIRST)   | W |   | 1 K x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 1,1,1           |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.

Distributed RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|Module Name                                                               | RTL Object                                       | Inference | Size (Depth x Width) | Primitives     |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | valid_mem_reg                                    | Implied   | 512 x 1              | RAM256X1D x 2  |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M16 x 1   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M16 x 3   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M16 x 3   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M16 x 2   |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl:23]
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl:23]
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl:23]
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:06:15 ; elapsed = 00:06:35 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41207 ; free virtual = 54077
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:06:19 ; elapsed = 00:06:39 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41149 ; free virtual = 54019
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Final Mapping Report
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name                                                               | RTL Object                                    | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|core_inst/eth_mac_10g_fifo_inst                                           | tx_fifo/fifo_inst/mem_reg                     | 512 x 74(NO_CHANGE)    | W |   | 512 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/eth_mac_10g_fifo_inst                                           | rx_fifo/fifo_inst/mem_reg                     | 512 x 74(NO_CHANGE)    | W |   | 512 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | ip_addr_mem_reg                               | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      |                 |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | mac_addr_mem_reg                              | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      |                 |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/payload_fifo/mem_reg | 256 x 74(READ_FIRST)   | W |   | 256 x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      |                 |
|core_inst/udp_payload_fifo                                                | mem_reg                                       | 1 K x 74(READ_FIRST)   | W |   | 1 K x 74(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 1,1,1           |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+


Distributed RAM: Final Mapping Report
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|Module Name                                                               | RTL Object                                       | Inference | Size (Depth x Width) | Primitives     |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | valid_mem_reg                                    | Implied   | 512 x 1              | RAM256X1D x 2  |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M16 x 1   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M16 x 3   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M16 x 3   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M16 x 2   |
|core_inst/udp_complete_inst/udp_64_inst                                   | udp_checksum_gen_64_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M16 x 2   |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:06:22 ; elapsed = 00:06:42 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:06:26 ; elapsed = 00:06:46 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:06:26 ; elapsed = 00:06:46 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:27 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:06:27 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:06:27 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:06:27 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+------+--------------------+----------+
|      |BlackBox name       |Instances |
+------+--------------------+----------+
|1     |eth_xcvr_gt_full    |         1|
|2     |eth_xcvr_gt_channel |         3|
+------+--------------------+----------+

Report Cell Usage:
+------+--------------------+------+
|      |Cell                |Count |
+------+--------------------+------+
|1     |eth_xcvr_gt_channel |     3|
|4     |eth_xcvr_gt_full    |     1|
|5     |BUFG                |     2|
|6     |CARRY8              |    80|
|7     |IBUFDS_GTE4         |     1|
|8     |LUT1                |   138|
|9     |LUT2                |   711|
|10    |LUT3                |  1059|
|11    |LUT4                |   998|
|12    |LUT5                |  1145|
|13    |LUT6                |  2440|
|14    |MMCME4_BASE         |     1|
|15    |MUXF7               |    11|
|16    |MUXF8               |     2|
|17    |RAM256X1D           |     2|
|18    |RAM32M16            |     9|
|19    |RAM32X1D            |     2|
|20    |RAMB18E2            |     5|
|24    |RAMB36E2            |     6|
|28    |FDCE                |     4|
|29    |FDPE                |    26|
|30    |FDRE                |  5621|
|31    |FDSE                |   281|
|32    |IBUF                |     1|
|33    |IBUFGDS             |     1|
|34    |OBUF                |    14|
+------+--------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:06:27 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.449 ; gain = 3606.773 ; free physical = 41154 ; free virtual = 54023
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 14 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:06:23 ; elapsed = 00:06:45 . Memory (MB): peak = 6324.359 ; gain = 3491.848 ; free physical = 47328 ; free virtual = 60198
Synthesis Optimization Complete : Time (s): cpu = 00:06:31 ; elapsed = 00:06:52 . Memory (MB): peak = 6324.359 ; gain = 3610.684 ; free physical = 47328 ; free virtual = 60199
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6324.359 ; gain = 0.000 ; free physical = 47328 ; free virtual = 60199
INFO: [Netlist 29-17] Analyzing 111 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_0 has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_1 has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-326] The CLKFBOUT to CLKFBIN net for instance clk_mmcm_inst with COMPENSATION=INTERNAL is optimized away to aid design routability
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6344.461 ; gain = 0.000 ; free physical = 47276 ; free virtual = 60146
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 18 instances were transformed.
  BUFG => BUFGCE: 2 instances
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
  IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
  MMCME4_BASE => MMCME4_ADV: 1 instance
  RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
  RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances

Synth Design complete, checksum: 8d59c22b
INFO: [Common 17-83] Releasing license: Synthesis
255 Infos, 217 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:37 ; elapsed = 00:06:59 . Memory (MB): peak = 6344.461 ; gain = 3638.789 ; free physical = 47490 ; free virtual = 60361
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/synth_1/fpga.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:18:04 2023...
[Tue Feb 14 09:18:08 2023] synth_1 finished
wait_on_runs: Time (s): cpu = 00:08:28 ; elapsed = 00:08:03 . Memory (MB): peak = 2766.707 ; gain = 0.000 ; free physical = 50289 ; free virtual = 63131
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:18:08 2023...
echo "open_project fpga.xpr" > run_impl.tcl
echo "reset_run impl_1" >> run_impl.tcl
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
echo "wait_on_run impl_1" >> run_impl.tcl
echo "open_run impl_1" >> run_impl.tcl
echo "report_utilization -file fpga_utilization.rpt" >> run_impl.tcl
echo "report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt" >> run_impl.tcl
vivado -nojournal -nolog -mode batch -source run_impl.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_impl.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# reset_run impl_1
# launch_runs -jobs 4 impl_1
[Tue Feb 14 09:18:21 2023] Launched impl_1...
Run output will be captured here: /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/runme.log
# wait_on_run impl_1
[Tue Feb 14 09:18:21 2023] Waiting for impl_1 to finish...

*** Running vivado
    with args -log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source fpga.tcl -notrace
Command: link_design -top fpga -part xczu9eg-ffvb1156-2-e
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [Project 1-454] Reading design checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.dcp' for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.dcp' for cell 'sfp1_phy_inst/xcvr.eth_xcvr_gt_channel_inst'
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2705.676 ; gain = 0.000 ; free physical = 49930 ; free virtual = 62772
INFO: [Netlist 29-17] Analyzing 125 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/synth/eth_xcvr_gt_full.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst/inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/synth/eth_xcvr_gt_full.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst/inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp1_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp1_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp2_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp2_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp3_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc] for cell 'sfp3_phy_inst/xcvr.eth_xcvr_gt_channel_inst/inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_10g_fifo_inst
WARNING: [Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg\[\d+\]'. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
WARNING: [Vivado 12-180] No cells matched '.*/tx_sync_reg_[1234]_reg\[\d+\]'. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
INFO: [Timing 38-2] Deriving generated clocks [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
Inserting timing constraints for sync_reset instance sync_reset_125mhz_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/tx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp1_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp2_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp3_phy_inst/rx_reset_sync_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/ZCU102/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.531 ; gain = 0.000 ; free physical = 49631 ; free virtual = 62473
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 15 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
  IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
  RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
  RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances

18 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3085.531 ; gain = 379.855 ; free physical = 49631 ; free virtual = 62473
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3141.559 ; gain = 48.023 ; free physical = 49630 ; free virtual = 62473

Starting Cache Timing Information Task
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2785c36cb

Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3141.559 ; gain = 0.000 ; free physical = 49627 ; free virtual = 62470

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-1287] Pulled Inverter core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst/mem_reg_0_i_2 into driver instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst/mem_reg_0_i_5, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_0_i_2__0 into driver instance core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_0_i_5__0, which resulted in an inversion of 13 pins
INFO: [Opt 31-1287] Pulled Inverter core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_eth_rx_inst/cache_write_request_ip_reg[31]_i_1 into driver instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_eth_rx_inst/outgoing_eth_dest_mac_reg[47]_i_5, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter core_inst/udp_payload_fifo/mem_reg_bram_0_i_1 into driver instance core_inst/udp_payload_fifo/mem_reg_bram_0_i_5, which resulted in an inversion of 3 pins
INFO: [Opt 31-1287] Pulled Inverter sfp0_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/error_count_reg[3]_i_2 into driver instance sfp0_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/serdes_rx_reset_req_reg_i_2, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter sfp1_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/error_count_reg[3]_i_2__0 into driver instance sfp1_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/serdes_rx_reset_req_reg_i_2__0, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter sfp2_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/error_count_reg[3]_i_2__2 into driver instance sfp2_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/serdes_rx_reset_req_reg_i_2__2, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter sfp3_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/error_count_reg[3]_i_2__1 into driver instance sfp3_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/serdes_rx_reset_req_reg_i_2__1, which resulted in an inversion of 5 pins
INFO: [Opt 31-138] Pushed 26 inverter(s) to 140 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1d264415c

Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49398 ; free virtual = 62241
INFO: [Opt 31-389] Phase Retarget created 16 cells and removed 50 cells
INFO: [Opt 31-1021] In phase Retarget, 60 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 15d031fda

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.4 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49398 ; free virtual = 62241
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 12 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 19c7b1361

Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.59 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49398 ; free virtual = 62241
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 37 cells

Phase 4 BUFG optimization
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
Phase 4 BUFG optimization | Checksum: 19c7b1361

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49397 ; free virtual = 62240
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 19c7b1361

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.67 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49397 ; free virtual = 62240
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 19c7b1361

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49397 ; free virtual = 62240
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              16  |              50  |                                             60  |
|  Constant propagation         |               0  |              12  |                                              0  |
|  Sweep                        |               0  |              37  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49397 ; free virtual = 62240
Ending Logic Optimization Task | Checksum: f54713c3

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3340.691 ; gain = 0.000 ; free physical = 49397 ; free virtual = 62240

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 2 BRAM(s) out of a total of 11 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 4 newly gated: 2 Total Ports: 22
Ending PowerOpt Patch Enables Task | Checksum: 25f0a8ddc

Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4962.902 ; gain = 0.000 ; free physical = 48405 ; free virtual = 61382
Ending Power Optimization Task | Checksum: 25f0a8ddc

Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 4962.902 ; gain = 1622.211 ; free physical = 48436 ; free virtual = 61413

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 25f0a8ddc

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4962.902 ; gain = 0.000 ; free physical = 48436 ; free virtual = 61413

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4962.902 ; gain = 0.000 ; free physical = 48436 ; free virtual = 61413
Ending Netlist Obfuscation Task | Checksum: 29d9fa173

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4962.902 ; gain = 0.000 ; free physical = 48436 ; free virtual = 61413
INFO: [Common 17-83] Releasing license: Implementation
64 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 4962.902 ; gain = 1877.371 ; free physical = 48436 ; free virtual = 61413
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4962.902 ; gain = 0.000 ; free physical = 48416 ; free virtual = 61400
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
Command: report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48359 ; free virtual = 61342
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d542fe2b

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48359 ; free virtual = 61342
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48359 ; free virtual = 61342

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11e25f13b

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48355 ; free virtual = 61343

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 206514c34

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48310 ; free virtual = 61299

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 206514c34

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48310 ; free virtual = 61299
Phase 1 Placer Initialization | Checksum: 206514c34

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48310 ; free virtual = 61299

Phase 2 Global Placement

Phase 2.1 Floorplanning

Phase 2.1.1 Partition Driven Placement

Phase 2.1.1.1 PBP: Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 1fb388ab6

Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48306 ; free virtual = 61296

Phase 2.1.1.2 PBP: Clock Region Placement
Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 1fb388ab6

Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 4986.914 ; gain = 0.000 ; free physical = 48272 ; free virtual = 61262

Phase 2.1.1.3 PBP: Compute Congestion
Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 1fb388ab6

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5001.262 ; gain = 14.348 ; free physical = 48196 ; free virtual = 61239

Phase 2.1.1.4 PBP: UpdateTiming
Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238

Phase 2.1.1.5 PBP: Add part constraints
Phase 2.1.1.5 PBP: Add part constraints | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238
Phase 2.1.1 Partition Driven Placement | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238
Phase 2.1 Floorplanning | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1950c1157

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48195 ; free virtual = 61238

Phase 2.4 Global Placement Core

Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 280 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 100 nets or LUTs. Breaked 0 LUT, combined 100 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-69] No nets found for rewiring optimization.
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5031.277 ; gain = 0.000 ; free physical = 48152 ; free virtual = 61197

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |            100  |                   100  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Equivalent Driver Rewiring                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |            100  |                   100  |           0  |           5  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.1 Physical Synthesis In Placer | Checksum: 103159292

Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48152 ; free virtual = 61197
Phase 2.4 Global Placement Core | Checksum: 13354199d

Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48142 ; free virtual = 61187
Phase 2 Global Placement | Checksum: 13354199d

Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 5031.277 ; gain = 44.363 ; free physical = 48148 ; free virtual = 61193

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1c9719f61

Time (s): cpu = 00:00:43 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48147 ; free virtual = 61192

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e29fc8bd

Time (s): cpu = 00:00:44 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48141 ; free virtual = 61187

Phase 3.3 Small Shape DP

Phase 3.3.1 Small Shape Clustering
Phase 3.3.1 Small Shape Clustering | Checksum: 1c5c2c94d

Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48140 ; free virtual = 61185

Phase 3.3.2 Flow Legalize Slice Clusters
Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: f5d4b6ae

Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48140 ; free virtual = 61185

Phase 3.3.3 Slice Area Swap

Phase 3.3.3.1 Slice Area Swap Initial
Phase 3.3.3.1 Slice Area Swap Initial | Checksum: 11b5a8058

Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48120 ; free virtual = 61166
Phase 3.3.3 Slice Area Swap | Checksum: 11b5a8058

Time (s): cpu = 00:00:46 ; elapsed = 00:00:20 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48099 ; free virtual = 61145
Phase 3.3 Small Shape DP | Checksum: 21a1496f4

Time (s): cpu = 00:00:49 ; elapsed = 00:00:21 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48130 ; free virtual = 61176

Phase 3.4 Re-assign LUT pins
Phase 3.4 Re-assign LUT pins | Checksum: 13e9bf8de

Time (s): cpu = 00:00:49 ; elapsed = 00:00:21 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48130 ; free virtual = 61176

Phase 3.5 Pipeline Register Optimization
Phase 3.5 Pipeline Register Optimization | Checksum: 13ff34094

Time (s): cpu = 00:00:49 ; elapsed = 00:00:22 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48130 ; free virtual = 61176
Phase 3 Detail Placement | Checksum: 13ff34094

Time (s): cpu = 00:00:49 ; elapsed = 00:00:22 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48130 ; free virtual = 61176

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 17ae7dc96

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 6 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.129 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 18835edf3

Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48119 ; free virtual = 61164
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 18a59cb94

Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48119 ; free virtual = 61164
Phase 4.1.1.1 BUFG Insertion | Checksum: 17ae7dc96

Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48119 ; free virtual = 61164

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.129. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: edf9f0ff

Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48119 ; free virtual = 61164

Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48119 ; free virtual = 61164
Phase 4.1 Post Commit Optimization | Checksum: edf9f0ff

Time (s): cpu = 00:00:56 ; elapsed = 00:00:24 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48119 ; free virtual = 61164
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48097 ; free virtual = 61143

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1c1cb6c5e

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
 ________________________________________________________________________
|           | Global Congestion | Long Congestion   | Short Congestion  |
| Direction | Region Size       | Region Size       | Region Size       |
|___________|___________________|___________________|___________________|
|      North|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|      South|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|       East|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|       West|                1x1|                1x1|                4x4|
|___________|___________________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1c1cb6c5e

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159
Phase 4.3 Placer Reporting | Checksum: 1c1cb6c5e

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48113 ; free virtual = 61159

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d6019892

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159
Ending Placer Task | Checksum: 1aa04cfdf

Time (s): cpu = 00:01:04 ; elapsed = 00:00:31 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48113 ; free virtual = 61159
INFO: [Common 17-83] Releasing license: Implementation
116 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:07 ; elapsed = 00:00:32 . Memory (MB): peak = 5047.285 ; gain = 60.371 ; free physical = 48279 ; free virtual = 61325
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.42 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48258 ; free virtual = 61322
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file fpga_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.3 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48226 ; free virtual = 61277
INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_placed.rpt -pb fpga_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file fpga_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48242 ; free virtual = 61293
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
125 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48206 ; free virtual = 61276
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: bb0e91eb ConstDB: 0 ShapeSum: 1b24c295 RouteDB: d3d17b5f
Nodegraph reading from file.  Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.53 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48081 ; free virtual = 61140
Post Restoration Checksum: NetGraph: 5051438 NumContArr: 650b7f80 Constraints: ab243c1e Timing: 0
Phase 1 Build RT Design | Checksum: 11534cfd6

Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48086 ; free virtual = 61146

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 11534cfd6

Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48042 ; free virtual = 61102

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 11534cfd6

Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48042 ; free virtual = 61102

Phase 2.3 Global Clock Net Routing
 Number of Nodes with overlaps = 0
Phase 2.3 Global Clock Net Routing | Checksum: e8bdc69e

Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48059 ; free virtual = 61119

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 2e03834f4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48057 ; free virtual = 61117
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.213  | TNS=0.000  | WHS=-0.189 | THS=-25.850|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 292c37ea9

Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48047 ; free virtual = 61108
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.213  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 2fc50bc0a

Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48044 ; free virtual = 61107

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000826758 %
  Global Horizontal Routing Utilization  = 0.00062152 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 11823
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 9396
  Number of Partially Routed Nets     = 2427
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 2d0a9bf9f

Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48031 ; free virtual = 61095

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2d0a9bf9f

Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48031 ; free virtual = 61095
Phase 3 Initial Routing | Checksum: 1a96892cd

Time (s): cpu = 00:00:24 ; elapsed = 00:00:11 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48006 ; free virtual = 61069

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2545
 Number of Nodes with overlaps = 218
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.859  | TNS=0.000  | WHS=-0.022 | THS=-0.022 |

Phase 4.1 Global Iteration 0 | Checksum: 1b28a8c95

Time (s): cpu = 00:00:38 ; elapsed = 00:00:17 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47977 ; free virtual = 61041

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.859  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 1f8de45c2

Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037
Phase 4 Rip-up And Reroute | Checksum: 1f8de45c2

Time (s): cpu = 00:00:40 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 26494325a

Time (s): cpu = 00:00:40 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 26494325a

Time (s): cpu = 00:00:40 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037
Phase 5 Delay and Skew Optimization | Checksum: 26494325a

Time (s): cpu = 00:00:40 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1ec64a49a

Time (s): cpu = 00:00:42 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.859  | TNS=0.000  | WHS=0.013  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:42 ; elapsed = 00:00:18 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037
Phase 6 Post Hold Fix | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:42 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.440753 %
  Global Horizontal Routing Utilization  = 0.551909 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:43 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:43 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:44 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 10 Resolve XTalk
Phase 10 Resolve XTalk | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:44 ; elapsed = 00:00:19 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037

Phase 11 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.859  | TNS=0.000  | WHS=0.013  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 11 Post Router Timing | Checksum: 1cfe6ccfe

Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47973 ; free virtual = 61037
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48038 ; free virtual = 61102

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
141 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:21 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48038 ; free virtual = 61102
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.49 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 48032 ; free virtual = 61117
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
Command: report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
Command: report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 6 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/victor/verilog-ethernet/example/ZCU102/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
Command: report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:24]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:30]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:40]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:53]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:62]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:64]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga.xdc:110]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
168 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 5047.285 ; gain = 0.000 ; free physical = 47980 ; free virtual = 61058
INFO: [runtcl-4] Executing : report_route_status -file fpga_route_status.rpt -pb fpga_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fpga_timing_summary_routed.rpt -pb fpga_timing_summary_routed.pb -rpx fpga_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_incremental_reuse -file fpga_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file fpga_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fpga_bus_skew_routed.rpt -pb fpga_bus_skew_routed.pb -rpx fpga_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:20:27 2023...
[Tue Feb 14 09:20:33 2023] impl_1 finished
wait_on_runs: Time (s): cpu = 00:00:01 ; elapsed = 00:02:12 . Memory (MB): peak = 2721.680 ; gain = 0.000 ; free physical = 50901 ; free virtual = 63986
# open_run impl_1
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2722.680 ; gain = 0.000 ; free physical = 50079 ; free virtual = 63164
INFO: [Netlist 29-17] Analyzing 125 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF Files: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.5 . Memory (MB): peak = 3065.352 ; gain = 27.781 ; free physical = 49695 ; free virtual = 62781
Restored from archive | CPU: 0.510000 secs | Memory: 13.914581 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3065.352 ; gain = 27.781 ; free physical = 49695 ; free virtual = 62781
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3450.016 ; gain = 0.000 ; free physical = 49318 ; free virtual = 62404
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 15 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
  IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
  RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
  RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances

open_run: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3450.016 ; gain = 728.336 ; free physical = 49318 ; free virtual = 62404
# report_utilization -file fpga_utilization.rpt
# report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:20:53 2023...
echo "open_project fpga.xpr" > generate_bit.tcl
echo "open_run impl_1" >> generate_bit.tcl
echo "write_bitstream -force fpga.runs/impl_1/fpga.bit" >> generate_bit.tcl
echo "write_debug_probes -force fpga.runs/impl_1/fpga.ltx" >> generate_bit.tcl
vivado -nojournal -nolog -mode batch -source generate_bit.tcl

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source generate_bit.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# open_run impl_1
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2705.676 ; gain = 0.000 ; free physical = 50083 ; free virtual = 63168
INFO: [Netlist 29-17] Analyzing 125 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF Files: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.5 . Memory (MB): peak = 3063.355 ; gain = 26.812 ; free physical = 49699 ; free virtual = 62785
Restored from archive | CPU: 0.510000 secs | Memory: 13.914581 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3063.355 ; gain = 26.812 ; free physical = 49699 ; free virtual = 62785
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3447.020 ; gain = 0.000 ; free physical = 49322 ; free virtual = 62408
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 15 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
  IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
  RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
  RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances

open_run: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3447.020 ; gain = 741.344 ; free physical = 49322 ; free virtual = 62408
# write_bitstream -force fpga.runs/impl_1/fpga.bit
Command: write_bitstream -force fpga.runs/impl_1/fpga.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 6 threads
WARNING: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_1) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
WARNING: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst/mem_reg_0) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 6 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 151878432 bits.
Writing bitstream fpga.runs/impl_1/fpga.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
8 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 4001.180 ; gain = 554.160 ; free physical = 49225 ; free virtual = 62319
# write_debug_probes -force fpga.runs/impl_1/fpga.ltx
INFO: [Chipscope 16-244] No debug cores were found in this design.
INFO: [Common 17-206] Exiting Vivado at Tue Feb 14 09:21:48 2023...
ln -f -s fpga.runs/impl_1/fpga.bit .
if [ -e fpga.runs/impl_1/fpga.ltx ]; then ln -f -s fpga.runs/impl_1/fpga.ltx .; fi
mkdir -p rev
COUNT=100; \
while [ -e rev/fpga_rev$COUNT.bit ]; \
do COUNT=$((COUNT+1)); done; \
cp -pv fpga.runs/impl_1/fpga.bit rev/fpga_rev$COUNT.bit; \
if [ -e fpga.runs/impl_1/fpga.ltx ]; then cp -pv fpga.runs/impl_1/fpga.ltx rev/fpga_rev$COUNT.ltx; fi
'fpga.runs/impl_1/fpga.bit' -> 'rev/fpga_rev100.bit'
make[1]: Leaving directory '/home/victor/verilog-ethernet/example/ZCU102/fpga/fpga'

[alexforencich]

Took a look at the KR260 schematic; it looks like porting the design from the ZCU102 should mainly be a matter of updating the pin constraints and deleting 3 of the SFP+ channels. Although, it looks like there isn't an external 125 MHz clock (the GTH transceivers need a free-running clock of some sort) so maybe you can borrow the setup I have for the VCU1525 to take the transceiver ref clock and convert that to 125 MHz, see https://github.com/alexforencich/verilog-ethernet/blob/master/example/VCU1525/fpga_10g/rtl/fpga.v#L364 . I suppose using a PLL to convert to 125 MHz is not strictly necessary, the GTH transceivers would probably work fine with using the 156.25 MHz ref clock directly, but I like putting that PLL in so things are consistent. You'll need to adjust the PLL settings for 156.25 MHz as the VCU1525 uses 161.1328125 MHz. Looks like 156.25 * 8/10 = 125, so D = 1 and M = 8 for Fvco 1250 MHz, output divide = 10 to get 125 MHz, and set the input period to 6.4.

Also, it looks like the 156.25 MHz oscillator is fixed, which is a little unfortunate. Fine for PTP, but something like sync-e or white rabbit would need an adjustable oscillator like an si570 or PLL chip with ppb-resolution adjustment capability.

[alexforencich]

Actually, on taking another look at the KR260 schematic, it looks like there are 25 MHz clocks provided to the PL on two different pins (see page 16 on the sch). So, you could feed that into a PLL and covert it to 125 MHz, instead of using the 156.25 MHz from the ref osc. Either method would work, but if you want to make a 1G design it might make more sense to use one of those 25 MHz clocks instead of the GTH ref clock.

[vmayoral]

All right, so spent the last few weeks understanding and porting the code for the KR260. The branch that currently reflects my latest status is https://github.com/vmayoral/verilog-ethernet/tree/kr260. I've gone through quite a few iterations while using the following resources:

• Schematics
  • ZCU102 schematics (0381701r01.pdf)
  • KR260 schematics (038-05101-01_sck-kr_reva02_SKIT_20211015.pdf)
• User Guides
  • Kria SOM Carrier Card Design Guide
  • Kria KR260 Starter Kit User Guide
  • Kria K26 SOM Datasheet
  • ZCU102 Evaluation Board User Guide
  • K26 SOM XDC file

After jumping over quite a few hurdles, I bumped into DRC errors about a week ago and have been fighting with them ever since. Dropping my struggles in here for completeness:

Struggle 1

❌ (summary) LVCMOS33 I/O standard is not supported for banks of type High Performance

Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-86] Your Implementation license expires in 15 day(s)
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 6 threads
ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 66 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported for banks of type High Performance.  Move the following ports or change their properties:
sfp0_tx_disable_b
ERROR: [DRC PLHDIO-5] HDIO DRC Checks: The following IO terminals need to be placed in HIGH_DENSITY IO banks (based on their IO standards), but they are incorrectly locked to non-HIGH_DENSITY IO banks. Please review and update the LOC constraints:
sfp0_tx_disable_b
CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block IBUFDS_GTE4 cell ibufds_gte4_sfp_mgt_refclk_0_inst is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems.
INFO: [Vivado_Tcl 4-198] DRC finished with 2 Errors, 1 Critical Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
INFO: [Common 17-83] Releasing license: Implementation
67 Infos, 2 Warnings, 9 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

Complete error dump at https://gist.github.com/vmayoral/fe294556fe89ee18737ac706ee07c100

Struggle 2

If I bypass the previous error root cause, I bump into the following error which affects most of the definitions in the XDC:

❌ (summary) ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value

open_run: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3434.082 ; gain = 728.406 ; free physical = 44205 ; free virtual = 62105
# write_bitstream -force fpga.runs/impl_1/fpga.bit
Command: write_bitstream -force fpga.runs/impl_1/fpga.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-86] Your Implementation license expires in 15 day(s)
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 6 threads
ERROR: [DRC NSTD-1] Unspecified I/O Standard: 12 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[7:0], clk_125mhz_n, clk_125mhz_p, reset, and sfp0_tx_disable_b.
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 13 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led[7:0], clk_125mhz_n, clk_125mhz_p, reset, sfp_mgt_refclk_0_n, and sfp_mgt_refclk_0_p.
INFO: [Vivado 12-3199] DRC finished with 2 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
7 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
write_bitstream failed
write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3771.211 ; gain = 337.129 ; free physical = 44065 ; free virtual = 61965
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

Complete error dump at https://gist.github.com/vmayoral/b31084a9d7f93812a24b19e98e62be44

[alexforencich]

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 12 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[7:0], clk_125mhz_n, clk_125mhz_p, reset, and sfp0_tx_disable_b.
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 13 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[7:0], clk_125mhz_n, clk_125mhz_p, reset, sfp_mgt_refclk_0_n, and sfp_mgt_refclk_0_p.

Looks like maybe some of these signals should be removed from the top-level verilog file, and the ones that are necessary should get LOC and IOSTANDARD constraints.

ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 66 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported for banks of type High Performance. Move the following ports or change their properties:
sfp0_tx_disable_b
ERROR: [DRC PLHDIO-5] HDIO DRC Checks: The following IO terminals need to be placed in HIGH_DENSITY IO banks (based on their IO standards), but they are incorrectly locked to non-HIGH_DENSITY IO banks. Please review and update the LOC constraints:
sfp0_tx_disable_b

From looking at the schematic, this one makes no sense at all. The pin is pulled up to +3v3, but it looks like it's wired to a pin with Vccio of 1.8v, without any level shifting? That looks like a rather serious board design mistake, tbh. But if Vccio is 1.8, then use LVCMOS18.

CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block IBUFDS_GTE4 cell ibufds_gte4_sfp_mgt_refclk_0_inst is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems.

Looks like this didn't get any LOC constraints.

[vmayoral]

Thanks for all of the above @alexforencich,

I re-iterated based on this (and the rest of our discussion, so thanks!) resulting in:

• ✅ LED pins, removed the extra ones in the HDL vmayoral@00c8abf
• ⚠️ sfp0_tx_disable_b pulled up to +3v3, but it looks like it's wired to a pin with Vccio of 1.8V without level shifting. Using LVCMOS18 removed the error while building vmayoral@f2d3f07
• ✅ avoided using same pins to assign various things. Used the 25 MHz PL-connected clock and through a PLL generated the 125 MHz clock vmayoral@969ef0c
• ✅ Update IOSTANDARD of pins, Note the need to be mapping the K26 XDC, identify in there the corresponding VCCO and then, cross-reference that with the Datasheet of the KR260 board pin I/O vmayoral@af1f758

Final branch available at https://github.com/vmayoral/verilog-ethernet/tree/kr260. My expectation was for things to build just fine this time but still bumping into the following two errors:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 4 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[1:0], clk_25mhz_ref, and reset.

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 6 out of 11 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led[1:0], clk_25mhz_ref, reset, sfp_mgt_refclk_0_n, and sfp_mgt_refclk_0_p.

Further analyzing this:

• ❌ [DRC NSTD-1] Unspecified I/O Standard, typically indicates that a logical port in your design is not constrained to a physical location on the FPGA device. This is confusing since it's defined in the K26 SOM is XDC. Pins affected:
  • led[1:0]
  • clk_25mhz_ref,
  • reset
• ❌ [DRC UCIO-1] Unconstrained Logical Port, similar to above, hints that a logical port in your design is not constrained to a physical location on the FPGA device
  • led[1:0]
  • clk_25mhz_ref
  • reset
  • sfp_mgt_refclk_0_n
  • sfp_mgt_refclk_0_p

To my uderstanding, the definitions in the fgpa.xdc file should be enough as they refer to the K26 SOM (which sets the PACKAGE_PIN for every one them)

[vmayoral]

All right, managed to address the hurdles above after various iterations. One of the major issues being experienced is that though I had modified the part number in various places, I had overlooked the variable in the Makefile. So of course I was being driven nuts by pin conflicts. It was a different SoC after all. vmayoral@b084a8b did it.

• I've also removed the reset signal from the XDC and hardcoded that in the PLL vmayoral@4902d98#diff-2a694dcf8aeb602499f5e2bbc7b57eb3a05fa94f540abe61080008d6f86d2079R242
• Removed IOSTANDARD definitions from SFP MGT REFCLK pins to mitigate CRITICAL WARNINGS vmayoral@3700157#diff-0bfc7823308e66729fd6b8005b41707e964822e4b2c28416d70456e2adc2732dR128-R129

Bitstream builds just fine. However, when programming the PL (testing for now without SD card, to avoid any possible interference, will scale from there once functional) and testing the link:

victor@accelerationrobotics:~/verilog-ethernet/example/KR260/fpga/fpga$ sudo ethtool enp3s0
Settings for enp3s0:
	Supported ports: [ FIBRE ]
	Supported link modes:   10000baseT/Full
	Supported pause frame use: Symmetric
	Supports auto-negotiation: No
	Supported FEC modes: Not reported
	Advertised link modes:  10000baseT/Full
	Advertised pause frame use: Symmetric
	Advertised auto-negotiation: No
	Advertised FEC modes: Not reported
	Speed: Unknown!
	Duplex: Unknown! (255)
	Auto-negotiation: off
	Port: Direct Attach Copper
	PHYAD: 0
	Transceiver: internal
	Supports Wake-on: d
	Wake-on: d
        Current message level: 0x00000007 (7)
                               drv probe link
	Link detected: no

This hints there's something wrong with the design, since I can see the link up perfectly fine with the ZCU102 reference design. No CRITICAL WARNING. Looking at the WARNING messages through the logs, the following caught my attention:

./fpga.runs/synth_1/fpga.vds:WARNING: [Synth 8-3917] design fpga has port sfp0_tx_disable_b driven by constant 1

however that doesn't seem to be the issue, as I can see the same being reported and shown in the ZCU102 design, which is known and confirmed to work:

KR260 design	ZCU102 design

[alexforencich]

Well, one minor thing that should be fixed, although it should make no difference when using a DAC: the TX disable connection on the ZCU102 is inverted (there is a transistor in line that provides the level translation) and as such has a _b in the name and is tied to 1. But on the KR260, it's a direct connection, so the _b should be dropped and it should be tied to 0.

Now, as for why it's not working, we'll have to work through a few things. No link reported at the link partner definitely rules out a lot of possibilities. Start with the pinout report and the clock summary from the timing report. Make sure that all of the clock frequencies in the timing report are correct, and that everything is actually using the correct pins.

[alexforencich]

ummmm, this is likely a problem:

https://github.com/vmayoral/verilog-ethernet/blob/3700157745fbcf4559d4e39dd12a5037825dccc7/example/KR260/fpga/rtl/fpga.v#L242