Add example design for KCU105

example/KCU105/fpga_1g/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

example/KCU105/fpga_1g/README.md

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+# Verilog Ethernet KCU105 Example Design
+
+## Introduction
+
+This example design targets the Xilinx KCU105 FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+*  FPGA: xcku040-ffva1156-2-e
+*  PHY: Marvell M88E1111
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the KCU105 board with Vivado.  Then run
+
+    netcat -u 192.168.1.128 1234
+
+to open a UDP connection to port 1234.  Any text entered into netcat will be
+echoed back after pressing enter.
+
+It is also possible to use hping to test the design by running
+
+    hping 192.168.1.128 -2 -p 1234 -d 1024

example/KCU105/fpga_1g/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. KintexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcku040-ffva1156-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = KintexUltrascale
+# FPGA_DEVICE = xcku040-ffva1156-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+
+SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+else
+  XDC_FILES_REL = $(PROJECT).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi

example/KCU105/fpga_1g/fpga.xdc

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+# XDC constraints for the Xilinx KCU105 board
+# part: xcku040-ffva1156-2-e
+
+# General configuration
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+# 125 MHz
+set_property -dict {LOC G10  IOSTANDARD LVDS} [get_ports clk_125mhz_p]
+set_property -dict {LOC F10  IOSTANDARD LVDS} [get_ports clk_125mhz_n]
+create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
+
+
+# LEDs
+set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
+set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
+set_property -dict {LOC P20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
+set_property -dict {LOC P21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
+set_property -dict {LOC N22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
+set_property -dict {LOC M22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
+set_property -dict {LOC R23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
+set_property -dict {LOC P23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Reset button
+set_property -dict {LOC AN8  IOSTANDARD LVCMOS18} [get_ports reset]
+
+set_false_path -from [get_ports {reset}]
+set_input_delay 0 [get_ports {reset}]
+
+# Push buttons
+set_property -dict {LOC AF8  IOSTANDARD LVCMOS18} [get_ports btnu]
+set_property -dict {LOC AF9  IOSTANDARD LVCMOS18} [get_ports btnl]
+set_property -dict {LOC AD10  IOSTANDARD LVCMOS18} [get_ports btnd]
+set_property -dict {LOC AE8  IOSTANDARD LVCMOS18} [get_ports btnr]
+set_property -dict {LOC AE10 IOSTANDARD LVCMOS18} [get_ports btnc]
+
+set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
+set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
+
+# DIP switches
+set_property -dict {LOC AN16  IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
+set_property -dict {LOC AN19  IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
+set_property -dict {LOC AP18  IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
+set_property -dict {LOC AN14  IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# UART
+set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
+set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
+set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
+set_property -dict {LOC L23 IOSTANDARD LVCMOS18} [get_ports uart_cts]
+
+set_false_path -to [get_ports {uart_txd uart_rts}]
+set_output_delay 0 [get_ports {uart_txd uart_rts}]
+set_false_path -from [get_ports {uart_rxd uart_cts}]
+set_input_delay 0 [get_ports {uart_rxd uart_cts}]
+
+# Gigabit Ethernet SGMII PHY
+set_property -dict {LOC P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p]
+set_property -dict {LOC N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p]
+set_property -dict {LOC P26 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_clk_p]
+set_property -dict {LOC J23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n]
+
+set_false_path -to [get_ports {phy_reset_n}]
+set_output_delay 0 [get_ports {phy_reset_n}]

example/KCU105/fpga_1g/fpga/Makefile

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+
+# FPGA settings
+FPGA_PART = xcku040-ffva1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = KintexUltrascale
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

example/KCU105/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl

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+
+create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0
+
+set_property -dict [list \
+    CONFIG.Standard {SGMII} \
+    CONFIG.Physical_Interface {LVDS} \
+    CONFIG.Management_Interface {false} \
+    CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
+    CONFIG.LvdsRefClk {625} \
+] [get_ips gig_ethernet_pcs_pma_0]

example/KCU105/fpga_1g/lib/eth

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+../../../../