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25 changes: 25 additions & 0 deletions example/KCU116/fpga_10g/Makefile
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# Targets
TARGETS:=

# Subdirectories
SUBDIRS = fpga
SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))

# Rules
.PHONY: all
all: $(SUBDIRS) $(TARGETS)

.PHONY: $(SUBDIRS)
$(SUBDIRS):
cd $@ && $(MAKE)

.PHONY: $(SUBDIRS_CLEAN)
$(SUBDIRS_CLEAN):
cd $(@:.clean=) && $(MAKE) clean

.PHONY: clean
clean: $(SUBDIRS_CLEAN)
-rm -rf $(TARGETS)

program:
#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
37 changes: 37 additions & 0 deletions example/KCU116/fpga_10g/README.md
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# Verilog Ethernet Xilinx KCU116 Example Design

## Introduction

This example design targets the Xilinx Kintex UltraScale+ KCU116 FPGA board.

The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly to
ARP requests. Only SFP0 works by default.

The reference clock for the GTY transceiver connected to the SFPs is generated
by an external, on-board Si5328 clock chip which must be configured to output a
clock signal of 156.25MHz before the transceiver can be used. This configuration
is performed through the onboard Zynq-based baseboard management
controller. Software for configuring the Zynq BMC and setting the proper clock
frequencies can be found on Xilinx' website.

* FPGA: XCKU5P-2FFVB676E
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver

## How to build

Run make to build. Ensure that the Xilinx Vivado toolchain components are in
PATH.

## How to test

Run make program to program the NetFPGA SUME board with Vivado. Then run

netcat -u 192.168.1.128 1234

to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.

It is also possible to use hping to test the design by running

hping 192.168.1.128 -2 -p 1234 -d 1024
123 changes: 123 additions & 0 deletions example/KCU116/fpga_10g/common/vivado.mk
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###################################################################
#
# Xilinx Vivado FPGA Makefile
#
# Copyright (c) 2016 Alex Forencich
#
###################################################################
#
# Parameters:
# FPGA_TOP - Top module name
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
# SYN_FILES - space-separated list of source files
# INC_FILES - space-separated list of include files
# XDC_FILES - space-separated list of timing constraint files
# XCI_FILES - space-separated list of IP XCI files
#
# Example:
#
# FPGA_TOP = fpga
# FPGA_FAMILY = VirtexUltrascale
# FPGA_DEVICE = xcvu095-ffva2104-2-e
# SYN_FILES = rtl/fpga.v
# XDC_FILES = fpga.xdc
# XCI_FILES = ip/pcspma.xci
# include ../common/vivado.mk
#
###################################################################

# phony targets
.PHONY: clean fpga

# prevent make from deleting intermediate files and reports
.PRECIOUS: %.xpr %.bit %.mcs %.prm
.SECONDARY:

CONFIG ?= config.mk
-include ../$(CONFIG)

SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))

ifdef XDC_FILES
XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
else
XDC_FILES_REL = $(FPGA_TOP).xdc
endif

###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and project files
###################################################################

all: fpga

fpga: $(FPGA_TOP).bit

vivado: $(FPGA_TOP).xpr
vivado $(FPGA_TOP).xpr

tmpclean:
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl

clean: tmpclean
-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl

distclean: clean
-rm -rf rev

###################################################################
# Target implementations
###################################################################

# Vivado project file
%.xpr: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
rm -rf defines.v
touch defines.v
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done
echo "exit" >> create_project.tcl
vivado -nojournal -nolog -mode batch -source create_project.tcl

# synthesis run
%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
echo "open_project $*.xpr" > run_synth.tcl
echo "reset_run synth_1" >> run_synth.tcl
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
echo "wait_on_run synth_1" >> run_synth.tcl
echo "exit" >> run_synth.tcl
vivado -nojournal -nolog -mode batch -source run_synth.tcl

# implementation run
%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
echo "open_project $*.xpr" > run_impl.tcl
echo "reset_run impl_1" >> run_impl.tcl
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
echo "wait_on_run impl_1" >> run_impl.tcl
echo "exit" >> run_impl.tcl
vivado -nojournal -nolog -mode batch -source run_impl.tcl

# bit file
%.bit: %.runs/impl_1/%_routed.dcp
echo "open_project $*.xpr" > generate_bit.tcl
echo "open_run impl_1" >> generate_bit.tcl
echo "write_bitstream -force $*.bit" >> generate_bit.tcl
echo "exit" >> generate_bit.tcl
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
mkdir -p rev
EXT=bit; COUNT=100; \
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
do COUNT=$$((COUNT+1)); done; \
cp $@ rev/$*_rev$$COUNT.$$EXT; \
echo "Output: rev/$*_rev$$COUNT.$$EXT";
67 changes: 67 additions & 0 deletions example/KCU116/fpga_10g/fpga.xdc
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# XDC constraints for the Xilinx Kintex UltraScale+ KCU116
# part: xcku5p-ffvb676-2-e

# General configuration
set_property CFGBVS GND [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]

# 300MHz sysclk
set_property -dict {LOC K22 IOSTANDARD DIFF_SSTL12 } [get_ports clk_300mhz_p];
set_property -dict {LOC K23 IOSTANDARD DIFF_SSTL12 } [get_ports clk_300mhz_n];

# LEDs
set_property -dict {LOC C9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[0]}]
set_property -dict {LOC D9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[1]}]
set_property -dict {LOC E10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[2]}]
set_property -dict {LOC E11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[3]}]
set_property -dict {LOC F9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[4]}]
set_property -dict {LOC F10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[5]}]
set_property -dict {LOC G9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[6]}]
set_property -dict {LOC G10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {user_led[7]}]

set_false_path -to [get_ports {user_led[*]}]
set_output_delay 0 [get_ports {user_led[*]}]

# SFP Interfaces
set_property -dict {LOC M2 } [get_ports sfp_0_rx_p];
set_property -dict {LOC M1 } [get_ports sfp_0_rx_n];
set_property -dict {LOC N5 } [get_ports sfp_0_tx_p];
set_property -dict {LOC N4 } [get_ports sfp_0_tx_n];
set_property -dict {LOC AB14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_0_tx_disable_n]

set_property -dict {LOC K2 } [get_ports sfp_1_rx_p];
set_property -dict {LOC K1 } [get_ports sfp_1_rx_n];
set_property -dict {LOC L5 } [get_ports sfp_1_tx_p];
set_property -dict {LOC L4 } [get_ports sfp_1_tx_n];
set_property -dict {LOC AA14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable_n]

set_property -dict {LOC H2 } [get_ports sfp_2_rx_p];
set_property -dict {LOC H1 } [get_ports sfp_2_rx_n];
set_property -dict {LOC J5 } [get_ports sfp_2_tx_p];
set_property -dict {LOC J4 } [get_ports sfp_2_tx_n];
set_property -dict {LOC AA15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable_n]

set_property -dict {LOC F2 } [get_ports sfp_3_rx_p];
set_property -dict {LOC F1 } [get_ports sfp_3_rx_n];
set_property -dict {LOC G5 } [get_ports sfp_3_tx_p];
set_property -dict {LOC G4 } [get_ports sfp_3_tx_n];
set_property -dict {LOC Y15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_3_tx_disable_n]

set_property -dict {LOC P7 } [get_ports sfp_mgt_refclk_p]; # Bank 226 - MGTREFCLK0P_226
set_property -dict {LOC P6 } [get_ports sfp_mgt_refclk_n]; # Bank 226 - MGTREFCLK0N_226

# 156.25 MHz MGT reference clock
create_clock -period 6.4 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]

set_false_path -to [get_ports { \
sfp_3_tx_disable_n \
sfp_2_tx_disable_n \
sfp_1_tx_disable_n \
sfp_0_tx_disable_n \
}]
set_output_delay 0 [get_ports { \
sfp_3_tx_disable_n \
sfp_2_tx_disable_n \
sfp_1_tx_disable_n \
sfp_0_tx_disable_n \
}]
58 changes: 58 additions & 0 deletions example/KCU116/fpga_10g/fpga/Makefile
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# FPGA settings
FPGA_PART = xcku5p-ffvb676-2-e
FPGA_TOP = fpga
FPGA_ARCH = kintexuplus

# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
SYN_FILES += lib/eth/rtl/udp_complete_64.v
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
SYN_FILES += lib/eth/rtl/udp_64.v
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
SYN_FILES += lib/eth/rtl/ip_complete_64.v
SYN_FILES += lib/eth/rtl/ip_64.v
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
SYN_FILES += lib/eth/rtl/arp.v
SYN_FILES += lib/eth/rtl/arp_cache.v
SYN_FILES += lib/eth/rtl/arp_eth_rx.v
SYN_FILES += lib/eth/rtl/arp_eth_tx.v
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v

# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

# IP
IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl

include ../common/vivado.mk
23 changes: 23 additions & 0 deletions example/KCU116/fpga_10g/ip/gtwizard_ultrascale_0.tcl
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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0

set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0]

set_property -dict [list \
CONFIG.CHANNEL_ENABLE {X0Y11 X0Y10 X0Y9 X0Y8} \
CONFIG.TX_MASTER_CHANNEL {X0Y8} \
CONFIG.RX_MASTER_CHANNEL {X0Y8} \
CONFIG.TX_LINE_RATE {10.3125} \
CONFIG.TX_REFCLK_FREQUENCY {156.25} \
CONFIG.TX_USER_DATA_WIDTH {64} \
CONFIG.TX_INT_DATA_WIDTH {64} \
CONFIG.RX_LINE_RATE {10.3125} \
CONFIG.RX_REFCLK_FREQUENCY {156.25} \
CONFIG.RX_USER_DATA_WIDTH {64} \
CONFIG.RX_INT_DATA_WIDTH {64} \
CONFIG.RX_REFCLK_SOURCE {X0Y11 clk0 X0Y10 clk0 X0Y9 clk0 X0Y8 clk0} \
CONFIG.TX_REFCLK_SOURCE {X0Y11 clk0 X0Y10 clk0 X0Y9 clk0 X0Y8 clk0} \
CONFIG.FREERUN_FREQUENCY {125} \
CONFIG.ENABLE_OPTIONAL_PORTS {rxpolarity_in txpolarity_in} \
] [get_ips gtwizard_ultrascale_0]

1 change: 1 addition & 0 deletions example/KCU116/fpga_10g/lib/eth
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