This repository contains the Nios V Example designs based on different Altera FPGA development kits.
The following table contains the list of Acronyms that the user may come across in the design details
| Acronym | Expansion |
|---|---|
| DMA | Direct Memory Access |
| OCM | On-Chip Memory |
| PIO | Parallel I/O |
| RTOS | Real Time Operating System |
| ECC | Error-Correcting Code |
| TCM | Tightly Coupled Memory |
| GHRD | Golden Hardware Reference Design |
| SSS | Simple Socket Server |
| CI | Custom Instrcution |
| CRC | Cyclic Redundancy Check |
There are three variants of the NiosV core:
a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
Example Designs using Nios V as the core based on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)
Development kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html
The following table contains the list of the designs on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/g | Nios V/g FPU Design | Nios V/g Processor-based design example with Floating Point Unit (FPU) on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile) Design details |
| 2 | Nios V/g | Nios V/g Tightly Coupled Memory (TCM) Design | This design is about how to use the TCM feature in Nios V/g Processor Design details |
| 3 | Nios V/m | Nios V/m Iperf Design | This design demonstrates Iperf server application running on the development kit interacting with Iperf client on remote host Design details |
| 4 | Nios V/m | Nios V/m Simple Socket Server (SSS) Design | This design demonstrates Simple Socket Server Application Design details |
Example Designs using Nios V as the core based on Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile)
Development kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf014.html
The following table contains the list of the designs on Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile)
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor Design details |
| 2 | Nios V/g | Nios V/g Custom Instruction (CI) Basic Operations Design | This design demonstrates basic arithmetic and logic operations using the custom instruction feature of the Nios® V/g processor Design details |
| 3 | Nios V/g | Nios V/g Custom Instruction (CI) Cyclic Redundency Check (CRC) Design | This design demonstrates the Cyclic Redundancy Check (CRC) algorithm using the custom instruction feature of the Nios® V/g processor Design details |
| 4 | Nios V/g | Nios V/g ECC | This design demonstrates the ECC Lite feature of the Nios® V/g core by injecting an error on the General-Purpose Register (GPR) via simulation Design details |
| 5 | Nios V/g | Nios V/g Helloworld Design | Nios V/g Processor-based Helloworld example design Design details |
| 6 | Nios V/c | Nios V/c PIO OCM test Design | Nios V/c Processor-based Helloworld and OCM memory test example design Design details |
| 7 | Nios V/m | Nios V/m DDR DMA OCM Memory Test | This design demonstrates Nios V/m Processor-based Memory Test design Example Design details |
| 8 | Nios V/m | Nios V/m DMA OCM Memory Test Design | This design demonstrates Nios V/m Processor-based Direct Memory Access (DMA) and On-Chip Memory (OCM) Test Design details |
| 9 | Nios V/m | Nios V/m EMIF Design | This design demonstrates Nios V/m Processor-based External Memory Interface (EMIF) data mover example design Design details |
| 10 | Nios V/m | Nios V/m ISR Test | This design demonstrates Nios V/m Processor-based Timer Interrupt design Example Design details |
| 11 | Nios V/m | Nios V/m Helloworld Design | Nios V/m Processor-based Helloworld example design Design details |
| 12 | Nios V/m | Nios V/m OCM Memory Test Design | Nios V/m Processor-based On-Chip Memory (OCM) Test design Design details |
| 13 | Nios V/m | Nios V/m PIO Design | This design demonstrates the transaction between the Nios® V processor and the PIO core Design details |
Example Designs using Nios V as the core based on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)
Development kit product page - https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf027-and-agf023.html
The following table contains the list of the designs on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/m | Nios V/m Transceiver Loopback design | This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile) Design details |
Refer to the documents in the following link for More information on the Nios V Processor core - https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html