Open
Description
Friday Sep 20, 2019 at 12:09 GMT
Originally opened as m-labs/nmigen#213
Develop tooling to help with non-trivial flow graphs. Somewhat like the old migen.flow scheme.
Features
- pipelining the components to get maximum throughput and minimum delay
- handle
stb-style interfaces where data is not constantly streamed but "blanked" - handle framed data that spans multiple clock cycles (
eofa.k.a.sop/eop): determine overall cycle periods - handle interfaces where different components in the graph need exclusive access to a shared resource (memory, shared data workspace) and access needs to be controlled by proper timing of the activity of a component.
- maybe handle
stb/ack-style interfaces and implement back-pressure to dynamically pace upstream components - maybe handle dynamically changing latencies
Implementation aspects/questions
- Each component (naming: block/actor/node?) would need to provide a latency matrix from its input to its output ports (group delay)
- Insert delays where required to compensate for unmatched latencies along different edges
- Framing: require constant frame size for the entire graph?
- Calculate cycle period for framed data (for constant frame size this is the slowest component in the graph) and generate counter(s) to trigger source components at the proper interval
- Provide verification processes for simulation that assert the correct timing pattern (of e.g. the
stbsignals) at the module boundaries. I.e. allow verification of the specified latency matrices. - "Latency" may be hard to define for some components. E.g. an IIR filter. Interpretation of latency matching can be very context dependent.
Use cases, prior art:
migen.flow- SAWG: composes dozens of DSP blocks (spline interpolators, CORDICs, FIR filters, limiters etc) into a RF flow graph. Annotates latencies manually, and compensates for them so that every closed path in the graph (consisting of directed and latency-annotated edges) has zero total latency.
- SU-Servo: pipelines the ADC sampling/transfer, the IIR processing and the DDS SPI transfer stages manually and inserts "restart" counters so that the entire pipeline restarts automatically at the right time. Uses tokens that get passed along with data to signal activity.
- c.f. RFNoC: RF network on a chip for the USRP SDR hardware, mixed with gnuradio.