back.{verilog,rtlil}: in convert(), accept a Component without ports

[whitequark]

Fixes #883.
Depends on amaranth-lang/rfcs#25.

[codecov]

Codecov Report

Merging #886 (bffaafc) into main (88cbf30) will decrease coverage by 0.12%.
Report is 7 commits behind head on main.
The diff coverage is 57.14%.

@@            Coverage Diff             @@
##             main     #886      +/-   ##
==========================================
- Coverage   83.90%   83.79%   -0.12%     
==========================================
  Files          53       54       +1     
  Lines        7588     7651      +63     
  Branches     1839     1860      +21     
==========================================
+ Hits         6367     6411      +44     
- Misses       1025     1042      +17     
- Partials      196      198       +2     

Files Changed	Coverage Δ
amaranth/back/rtlil.py	77.88% <18.18%> (-1.09%)	⬇️
amaranth/back/verilog.py	52.38% <25.00%> (-13.25%)	⬇️
amaranth/lib/wiring.py	100.00% <100.00%> (ø)

... and 7 files with indirect coverage changes

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[cr1901]

While testing this, I ran into some issues getting efbutils to compile. Consider the following MCVE:

from amaranth import Module, unsigned
from amaranth.lib.data import Union
from amaranth.lib.wiring import Signature, In, Out, Component, connect
from amaranth.back import verilog


class WriteData(Union):
    stream: unsigned(8)


SeqWriteStreamSignature = Signature({
    "data": Out(WriteData),
    "ready": In(1),
    "valid": Out(1)
})

SeqReadStreamSignature = Signature({
    "data": Out(8),
    "ready": In(1),
    "valid": Out(1)
})


class Wrapper(Component):
    wr: Out(SeqWriteStreamSignature)
    rd: In(SeqReadStreamSignature)

    def __init__(self, s):
        super().__init__()
        self.s = s

    def elaborate(self, plat):
        m = Module()

        m.submodules += self.s

        connect(m, self.s.wr, self.wr)
        connect(m, self.rd, self.s.rd)

        return m


class Inner(Component):
    wr: In(SeqWriteStreamSignature)
    rd: Out(SeqReadStreamSignature)

    def __init__(self):
        super().__init__()

    def elaborate(self, plat):
        m = Module()

        m.d.comb += [
            self.rd.data.eq(self.wr.data),
            self.wr.ready.eq(self.rd.ready),
            self.rd.valid.eq(self.wr.valid)
        ]

        return m


if __name__ == "__main__":
    s = Inner()
    m = Wrapper(s)

    print(verilog.convert(m))

This results in the following output:

/* Generated by Yosys 0.32+76 (git sha1 73cb4977b, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os) */

(* \amaranth.hierarchy  = "top.U$$0" *)
(* generator = "Amaranth" *)
module \U$$0 (wr__ready, wr__valid, rd__data, rd__ready, rd__valid, wr__data);
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] rd__data;
  wire [7:0] rd__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  input rd__ready;
  wire rd__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output rd__valid;
  wire rd__valid;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [7:0] wr__data;
  wire [7:0] wr__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output wr__ready;
  wire wr__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  input wr__valid;
  wire wr__valid;
  assign rd__valid = wr__valid;
  assign wr__ready = rd__ready;
  assign rd__data = wr__data;
endmodule

(* \amaranth.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "Amaranth" *)
module top(rd__ready, rd__valid, wr__ready, wr__valid, rd__data);
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_rd__data ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_rd__ready ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_rd__valid ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_wr__data ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_wr__ready ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_wr__valid ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] rd__data;
  wire [7:0] rd__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  input rd__ready;
  wire rd__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output rd__valid;
  wire rd__valid;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] wr__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  output wr__ready;
  wire wr__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev178+geda5669-py3-none-any/amaranth/lib/wiring.py:227" *)
  input wr__valid;
  wire wr__valid;
  \U$$0  \U$$0  (
    .rd__data(\U$$0_rd__data ),
    .rd__ready(\U$$0_rd__ready ),
    .rd__valid(\U$$0_rd__valid ),
    .wr__data(8'h00),
    .wr__ready(\U$$0_wr__ready ),
    .wr__valid(\U$$0_wr__valid )
  );
  assign wr__data = 8'h00;
  assign rd__valid = \U$$0_rd__valid ;
  assign \U$$0_rd__ready  = rd__ready;
  assign rd__data = \U$$0_rd__data ;
  assign \U$$0_wr__valid  = wr__valid;
  assign wr__ready = \U$$0_wr__ready ;
  assign \U$$0_wr__data  = 8'h00;
endmodule

Notice that the top-level port wr__data is missing/internally replaced with a constant assignment to 8'h00, but rd__data is not. wr__data was originally a Union, but rd__data was originally an unsigned shape.

[whitequark]

@cr1901 Should be working now!

[cr1901]

Can confirm it's working on my end now, on the exact same commit :).

[whitequark]

Thanks!