Add support for dumping structure fields in VCD #967
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See amaranth-lang#790. This commit adds an entirely private API for describing formatting of values that is used in the standard library, in departure from our standing policy of not using private APIs in the standard library. This is a temporary measure intended to get the version 0.4 released faster, as it has been years in the making. It is expected that this API will be made public in the version 0.5 after going through the usual RFC process. This commit only adds VCD lines for fields defined in `lib.data.Layout` when using `sim.pysim`. The emitted RTLIL and Verilog remain the same. It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will include aliases for layout fields as well. The value representation API also handles formatting of enumerations, with no changes visible to the designer. The implementation of `Signal(decoder=)` is changed as well to use the new API, with full backwards compatibility and no public API changes. Co-authored-by: Wanda <[email protected]>
This was referenced Nov 26, 2023
Codecov ReportAttention:
Additional details and impacted files@@ Coverage Diff @@
## main #967 +/- ##
==========================================
- Coverage 83.67% 83.61% -0.06%
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Files 54 55 +1
Lines 7784 7874 +90
Branches 1912 1934 +22
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+ Hits 6513 6584 +71
- Misses 1062 1079 +17
- Partials 209 211 +2 ☔ View full report in Codecov by Sentry. |
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We have discussed this PR, which adds a private API between the Amaranth AST and the Amaranth standard library, on the 2023-11-27 weekly meeting. The disposition was to merge with the understanding that the API will go through the RFC process before Amaranth 0.5. |
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See #790.
This PR adds an entirely private API for describing formatting of values that is used in the standard library, in departure from our standing policy of not using private APIs in the standard library.
This is a temporary measure intended to get the version 0.4 released faster, as it has been years in the making. It is expected that this API will be made public in the version 0.5 after going through the usual RFC process.
This PR only adds VCD lines for fields defined in
lib.data.Layoutwhen usingsim.pysim. The emitted RTLIL and Verilog remain the same. It is expected that whensim.cxxsimlands, RTLIL/Verilog output will include aliases for layout fields as well.The value representation API also handles formatting of enumerations, with no changes visible to the designer. The implementation of
Signal(decoder=)is changed as well to use the new API, with full backwards compatibility and no public API changes.