Encode ADIW/SDIW instructions correctly

[dylanmckay]

In the machine code generator, the ADIW and SDIW instructions encode their immediate operand as the source operand.

The instructions are defined like so:

let Constraints = "$src = $dst",
Defs = [SREG] in
def ADIWRdK : FWRdK<0b0,
                    (outs IWREGS:$dst),
                    (ins IWREGS:$src, i16imm:$src2),
                    "adiw\t$dst, $src2",
                    [(set IWREGS:$dst, (add IWREGS:$src, uimm6:$src2)),
                     (implicit SREG)]>;

There are three operands: $dst, $src, and $src2, with $dst being constrained to be the same register as $src.

In the FWRdK format:

class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
  : AVRInst16<outs, ins, asmstr, pattern>
{
  bits<5> d;    // mapped to dst register
  bits<6> K;    // mapped to immediate value

  let Inst{15-9} = 0b1001011;
  let Inst{8} = f;
  let Inst{7-6} = K{5-4};
  let Inst{5-4} = d{2-1};
  let Inst{3-0} = K{3-0};
}

$src and $dst are different operands, even though they are equal. d is mapped to the first operand, and K is mapped to the second. The first operand is actually $dst and the second is $src, and the third is the immediate value.

Thus, the register encoding is written when the immediate value should be, and the immediate value is ignored.

This is the code generated by tablegen:

    case AVR::ADIWRdK:
    case AVR::SBIWRdK: {
      // op: d
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(6)) << 3;
      // op: K
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(48)) << 2;
      Value |= op & UINT64_C(15);
      break;
    }

One way to fix the problem is to manually edit the

getMachineOpValue(MI, MI.getOperand(1), Fixups, STI)

into

getMachineOpValue(MI, MI.getOperand(2), Fixups, STI)

in the generated file, but this is not an acceptable solution.

This problem could have a simple solution, but I am still in the process of learning the tablegen format and there isn't much documentation.