Compile crash: "Don't know how to custom expand this!"

[4ntoine]

MBA-Anton:bin asmirnov$ ./clang -c -g -Os -Wall -ffunction-sections -fdata-sections -mmcu=atmega328p -DF_CPU=16000000L -MMD -DUSB_VID=null -DUSB_PID=null -DARDUINO=105 -I/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino -I/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/variants/standard -I/Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/avr/include --target=avr /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp -o /tmp/arduino_test1/HardwareSerial.cpp.o
In file included from /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp:32:
/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial_private.h:119:5: warning: 
      expression result unused; assign into a variable to force a volatile load
      [-Wunused-volatile-lvalue]
    *_udr;
    ^~~~~
Don't know how to custom expand this!
UNREACHABLE executed at /Users/asmirnov/Documents/dev/src/avr-llvm/llvm/lib/Target/AVR/AVRISelLowering.cpp:691!
0  clang-3.8                0x00000001081b93ee llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 46
1  clang-3.8                0x00000001081bacb9 PrintStackTraceSignalHandler(void*) + 25
2  clang-3.8                0x00000001081b79a9 llvm::sys::RunSignalHandlers() + 425
3  clang-3.8                0x00000001081bb03e SignalHandler(int) + 366
4  libsystem_platform.dylib 0x00007fff927d5f1a _sigtramp + 26
5  libsystem_platform.dylib 0x00007fff69f41764 _sigtramp + 3614881892
6  clang-3.8                0x00000001081bacdb raise + 27
7  clang-3.8                0x00000001081bad92 abort + 18
8  clang-3.8                0x00000001080fd326 llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 198
9  clang-3.8                0x0000000107159370 llvm::AVRTargetLowering::ReplaceNodeResults(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const + 96
10 clang-3.8                0x0000000108cf5b27 llvm::DAGTypeLegalizer::CustomLowerNode(llvm::SDNode*, llvm::EVT, bool) + 279
11 clang-3.8                0x0000000108cd5b49 llvm::DAGTypeLegalizer::ExpandIntegerResult(llvm::SDNode*, unsigned int) + 281
12 clang-3.8                0x0000000108cf2023 llvm::DAGTypeLegalizer::run() + 947
13 clang-3.8                0x0000000108cf83e2 llvm::SelectionDAG::LegalizeTypes() + 66
14 clang-3.8                0x0000000108e56761 llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 4193
15 clang-3.8                0x0000000108e556ef llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 255
16 clang-3.8                0x0000000108e553ca llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 5194
17 clang-3.8                0x0000000108e52ba6 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1142
18 clang-3.8                0x0000000107147a1b llvm::AVRDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 59
19 clang-3.8                0x00000001075b133e llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 110
20 clang-3.8                0x0000000107a3bd8d llvm::FPPassManager::runOnFunction(llvm::Function&) + 413
21 clang-3.8                0x0000000107a3c0a5 llvm::FPPassManager::runOnModule(llvm::Module&) + 117
22 clang-3.8                0x0000000107a3cac0 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) + 1392
23 clang-3.8                0x0000000107a3c366 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 310
24 clang-3.8                0x0000000107a3d241 llvm::legacy::PassManager::run(llvm::Module&) + 33
25 clang-3.8                0x0000000108411a8a (anonymous namespace)::EmitAssemblyHelper::EmitAssembly(clang::BackendAction, llvm::raw_pwrite_stream*) + 1866
26 clang-3.8                0x0000000108411172 clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, llvm::raw_pwrite_stream*) + 114
27 clang-3.8                0x00000001086848ef clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) + 1375
28 clang-3.8                0x00000001099111cf clang::ParseAST(clang::Sema&, bool, bool) + 1263
29 clang-3.8                0x0000000108a72a9a clang::ASTFrontendAction::ExecuteAction() + 522
30 clang-3.8                0x0000000108682d23 clang::CodeGenAction::ExecuteAction() + 3987
31 clang-3.8                0x0000000108a72000 clang::FrontendAction::Execute() + 112
32 clang-3.8                0x00000001089ecf1f clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 1023
33 clang-3.8                0x0000000108aec9a0 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 3200
34 clang-3.8                0x000000010711bdb8 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) + 4968
35 clang-3.8                0x000000010710e693 ExecuteCC1Tool(llvm::ArrayRef<char const*>, llvm::StringRef) + 163
36 clang-3.8                0x000000010710d325 main + 1573
37 libdyld.dylib            0x00007fff95ec05c9 start + 1
Stack dump:
0.  Program arguments: /Users/asmirnov/Documents/dev/src/avr-llvm/build/bin/clang-3.8 -cc1 -triple avr -emit-obj -disable-free -main-file-name HardwareSerial.cpp -mrelocation-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -target-cpu atmega328p -target-linker-version 242 -g -dwarf-column-info -ffunction-sections -fdata-sections -coverage-file /tmp/arduino_test1/HardwareSerial.cpp.o -resource-dir /Users/asmirnov/Documents/dev/src/avr-llvm/build/bin/../lib/clang/3.8.0 -dependency-file /tmp/arduino_test1/HardwareSerial.cpp.d -MT /tmp/arduino_test1/HardwareSerial.cpp.o -D F_CPU=16000000L -D USB_VID=null -D USB_PID=null -D ARDUINO=105 -I /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino -I /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/variants/standard -I /Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/avr/include -Os -Wall -fdeprecated-macro -fdebug-compilation-dir /Users/asmirnov/Documents/dev/src/avr-llvm/build/bin -ferror-limit 19 -fmessage-length 100 -mstackrealign -fobjc-runtime=gcc -fcxx-exceptions -fexceptions -fdiagnostics-show-option -fcolor-diagnostics -vectorize-loops -vectorize-slp -o /tmp/arduino_test1/HardwareSerial.cpp.o -x c++ /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp 
1.  <eof> parser at end of file
2.  Code generation
3.  Running pass 'Function Pass Manager' on module '/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp'.
4.  Running pass 'AVR DAG->DAG Instruction Selection' on function '@_ZN14HardwareSerial5beginEmh'
clang-3.8: error: unable to execute command: Illegal instruction: 4
clang-3.8: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 3.8.0 (https://github.com/avr-llvm/clang.git bc1779778787f8cfca43849f8a4412b5ca7432c1) (llvm/llvm.git 693f1d90faf67af7ca0ec14e3eb8643ac4a1972f)
Target: avr
Thread model: posix
clang-3.8: note: diagnostic msg: PLEASE submit a bug report to http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and associated run script.
clang-3.8: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-3.8: note: diagnostic msg: /var/folders/64/fwfkm1k51zbd4_c5lwpsbljh0000gn/T/HardwareSerial-33df4b.cpp
clang-3.8: note: diagnostic msg: /var/folders/64/fwfkm1k51zbd4_c5lwpsbljh0000gn/T/HardwareSerial-33df4b.sh
clang-3.8: note: diagnostic msg: 

********************

[dylanmckay]

Without debugging, I'm pretty certain that this issue is caused by #149. There are four Arduino files which use 32-bit division, and HardwareSerial0.cpp is one of them.

I recently added a special error message for this case - see here.

What revision of the compiler are you using?

Also, could you please run clang -S -emit-llvm -o HardwareSerial.ll and attach the IR as well.

[4ntoine]

MBA-Anton:bin asmirnov$ ./clang -version
clang-3.8: error: unknown argument: '-version'
clang-3.8: error: no input files
MBA-Anton:bin asmirnov$ ./clang --version
clang version 3.8.0 (https://github.com/avr-llvm/clang.git bc1779778787f8cfca43849f8a4412b5ca7432c1) (llvm/llvm.git 693f1d90faf67af7ca0ec14e3eb8643ac4a1972f)
Target: x86_64-apple-darwin14.3.0

[4ntoine]

./clang -S -emit-llvm -Wall -ffunction-sections -fdata-sections -mmcu=atmega328p -DF_CPU=16000000L -MMD -DUSB_VID=null -DUSB_PID=null -DARDUINO=105 -I/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino -I/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/variants/standard -I/Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/avr/include --target=avr /Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp -o /tmp/arduino_test1/HardwareSerial.ll

HardwareSerial.ll:

; ModuleID = '/Applications/Arduino.app/Contents/Resources/Java/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp'
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8"
target triple = "avr"

%class.HardwareSerial = type { %class.Stream, i8*, i8*, i8*, i8*, i8*, i8*, i8, i8, i8, i8, i8, [64 x i8], [64 x i8], i8 }
%class.Stream = type { %class.Print, i32, i32 }
%class.Print = type { i32 (...)**, i16 }

$_ZTS6Stream = comdat any

$_ZTI6Stream = comdat any

@_ZTV14HardwareSerial = unnamed_addr constant [8 x i8*] [i8* null, i8* bitcast ({ i8*, i8*, i8* }* @_ZTI14HardwareSerial to i8*), i8* bitcast (i16 (%class.HardwareSerial*, i8)* @_ZN14HardwareSerial5writeEh to i8*), i8* bitcast (i16 (%class.Print*, i8*, i16)* @_ZN5Print5writeEPKhj to i8*), i8* bitcast (i16 (%class.HardwareSerial*)* @_ZN14HardwareSerial9availableEv to i8*), i8* bitcast (i16 (%class.HardwareSerial*)* @_ZN14HardwareSerial4readEv to i8*), i8* bitcast (i16 (%class.HardwareSerial*)* @_ZN14HardwareSerial4peekEv to i8*), i8* bitcast (void (%class.HardwareSerial*)* @_ZN14HardwareSerial5flushEv to i8*)], align 2
@_ZTVN10__cxxabiv120__si_class_type_infoE = external global i8*
@_ZTS14HardwareSerial = constant [17 x i8] c"14HardwareSerial\00"
@_ZTS6Stream = linkonce_odr constant [8 x i8] c"6Stream\00", comdat
@_ZTI5Print = external constant i8*
@_ZTI6Stream = linkonce_odr constant { i8*, i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i16 2) to i8*), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @_ZTS6Stream, i32 0, i32 0), i8* bitcast (i8** @_ZTI5Print to i8*) }, comdat
@_ZTI14HardwareSerial = constant { i8*, i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i16 2) to i8*), i8* getelementptr inbounds ([17 x i8], [17 x i8]* @_ZTS14HardwareSerial, i32 0, i32 0), i8* bitcast ({ i8*, i8*, i8* }* @_ZTI6Stream to i8*) }

define weak void @_Z14serialEventRunv() #0 {
entry:
  br i1 icmp ne (i1 ()* @_Z17Serial0_availablev, i1 ()* null), label %land.lhs.true, label %if.end

land.lhs.true:                                    ; preds = %entry
  br i1 icmp ne (void ()* @_Z11serialEventv, void ()* null), label %land.lhs.true.1, label %if.end

land.lhs.true.1:                                  ; preds = %land.lhs.true
  %call = call zeroext i1 @_Z17Serial0_availablev()
  br i1 %call, label %if.then, label %if.end

if.then:                                          ; preds = %land.lhs.true.1
  call void @_Z11serialEventv()
  br label %if.end

if.end:                                           ; preds = %if.then, %land.lhs.true.1, %land.lhs.true, %entry
  ret void
}

declare extern_weak zeroext i1 @_Z17Serial0_availablev() #0

declare extern_weak void @_Z11serialEventv() #0

; Function Attrs: nounwind
define void @_ZN14HardwareSerial17_tx_udr_empty_irqEv(%class.HardwareSerial* %this) #1 align 2 {
entry:
  %this.addr = alloca %class.HardwareSerial*, align 2
  %c = alloca i8, align 1
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_tx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %0 = load volatile i8, i8* %_tx_buffer_tail, align 1
  %idxprom = zext i8 %0 to i16
  %_tx_buffer = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 13
  %arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* %_tx_buffer, i32 0, i16 %idxprom
  %1 = load i8, i8* %arrayidx, align 1
  store i8 %1, i8* %c, align 1
  %_tx_buffer_tail2 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %2 = load volatile i8, i8* %_tx_buffer_tail2, align 1
  %conv = zext i8 %2 to i16
  %add = add nsw i16 %conv, 1
  %rem = srem i16 %add, 64
  %conv3 = trunc i16 %rem to i8
  %_tx_buffer_tail4 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  store volatile i8 %conv3, i8* %_tx_buffer_tail4, align 1
  %3 = load i8, i8* %c, align 1
  %_udr = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 6
  %4 = load i8*, i8** %_udr, align 2
  store volatile i8 %3, i8* %4, align 1
  %_ucsra = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %5 = load i8*, i8** %_ucsra, align 2
  %6 = ptrtoint i8* %5 to i16
  %7 = inttoptr i16 %6 to i8*
  %8 = load volatile i8, i8* %7, align 1
  %conv5 = zext i8 %8 to i16
  %or = or i16 %conv5, 64
  %conv6 = trunc i16 %or to i8
  store volatile i8 %conv6, i8* %7, align 1
  %_tx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %9 = load volatile i8, i8* %_tx_buffer_head, align 1
  %conv7 = zext i8 %9 to i16
  %_tx_buffer_tail8 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %10 = load volatile i8, i8* %_tx_buffer_tail8, align 1
  %conv9 = zext i8 %10 to i16
  %cmp = icmp eq i16 %conv7, %conv9
  br i1 %cmp, label %if.then, label %if.end

if.then:                                          ; preds = %entry
  %_ucsrb = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %11 = load i8*, i8** %_ucsrb, align 2
  %12 = ptrtoint i8* %11 to i16
  %13 = inttoptr i16 %12 to i8*
  %14 = load volatile i8, i8* %13, align 1
  %conv10 = zext i8 %14 to i16
  %and = and i16 %conv10, -33
  %conv11 = trunc i16 %and to i8
  store volatile i8 %conv11, i8* %13, align 1
  br label %if.end

if.end:                                           ; preds = %if.then, %entry
  ret void
}

; Function Attrs: nounwind
define void @_ZN14HardwareSerial5beginEmh(%class.HardwareSerial* %this, i32 %baud, i8 zeroext %config) #1 align 2 {
entry:
  %this.addr = alloca %class.HardwareSerial*, align 2
  %baud.addr = alloca i32, align 2
  %config.addr = alloca i8, align 1
  %baud_setting = alloca i16, align 2
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  store i32 %baud, i32* %baud.addr, align 2
  store i8 %config, i8* %config.addr, align 1
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %0 = load i32, i32* %baud.addr, align 2
  %div = udiv i32 4000000, %0
  %sub = sub i32 %div, 1
  %div2 = udiv i32 %sub, 2
  %conv = trunc i32 %div2 to i16
  store i16 %conv, i16* %baud_setting, align 2
  %_ucsra = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %1 = load i8*, i8** %_ucsra, align 2
  store volatile i8 2, i8* %1, align 1
  %2 = load i32, i32* %baud.addr, align 2
  %cmp = icmp eq i32 %2, 57600
  br i1 %cmp, label %if.then, label %lor.lhs.false

lor.lhs.false:                                    ; preds = %entry
  %3 = load i16, i16* %baud_setting, align 2
  %cmp3 = icmp ugt i16 %3, 4095
  br i1 %cmp3, label %if.then, label %if.end

if.then:                                          ; preds = %lor.lhs.false, %entry
  %_ucsra4 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %4 = load i8*, i8** %_ucsra4, align 2
  store volatile i8 0, i8* %4, align 1
  %5 = load i32, i32* %baud.addr, align 2
  %div5 = udiv i32 2000000, %5
  %sub6 = sub i32 %div5, 1
  %div7 = udiv i32 %sub6, 2
  %conv8 = trunc i32 %div7 to i16
  store i16 %conv8, i16* %baud_setting, align 2
  br label %if.end

if.end:                                           ; preds = %if.then, %lor.lhs.false
  %6 = load i16, i16* %baud_setting, align 2
  %shr = lshr i16 %6, 8
  %conv9 = trunc i16 %shr to i8
  %_ubrrh = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 1
  %7 = load i8*, i8** %_ubrrh, align 2
  store volatile i8 %conv9, i8* %7, align 1
  %8 = load i16, i16* %baud_setting, align 2
  %conv10 = trunc i16 %8 to i8
  %_ubrrl = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 2
  %9 = load i8*, i8** %_ubrrl, align 2
  store volatile i8 %conv10, i8* %9, align 1
  %_written = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 7
  store i8 0, i8* %_written, align 1
  %10 = load i8, i8* %config.addr, align 1
  %_ucsrc = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 5
  %11 = load i8*, i8** %_ucsrc, align 2
  store volatile i8 %10, i8* %11, align 1
  %_ucsrb = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %12 = load i8*, i8** %_ucsrb, align 2
  %13 = ptrtoint i8* %12 to i16
  %14 = inttoptr i16 %13 to i8*
  %15 = load volatile i8, i8* %14, align 1
  %conv11 = zext i8 %15 to i16
  %or = or i16 %conv11, 16
  %conv12 = trunc i16 %or to i8
  store volatile i8 %conv12, i8* %14, align 1
  %_ucsrb13 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %16 = load i8*, i8** %_ucsrb13, align 2
  %17 = ptrtoint i8* %16 to i16
  %18 = inttoptr i16 %17 to i8*
  %19 = load volatile i8, i8* %18, align 1
  %conv14 = zext i8 %19 to i16
  %or15 = or i16 %conv14, 8
  %conv16 = trunc i16 %or15 to i8
  store volatile i8 %conv16, i8* %18, align 1
  %_ucsrb17 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %20 = load i8*, i8** %_ucsrb17, align 2
  %21 = ptrtoint i8* %20 to i16
  %22 = inttoptr i16 %21 to i8*
  %23 = load volatile i8, i8* %22, align 1
  %conv18 = zext i8 %23 to i16
  %or19 = or i16 %conv18, 128
  %conv20 = trunc i16 %or19 to i8
  store volatile i8 %conv20, i8* %22, align 1
  %_ucsrb21 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %24 = load i8*, i8** %_ucsrb21, align 2
  %25 = ptrtoint i8* %24 to i16
  %26 = inttoptr i16 %25 to i8*
  %27 = load volatile i8, i8* %26, align 1
  %conv22 = zext i8 %27 to i16
  %and = and i16 %conv22, -33
  %conv23 = trunc i16 %and to i8
  store volatile i8 %conv23, i8* %26, align 1
  ret void
}

; Function Attrs: nounwind
define void @_ZN14HardwareSerial3endEv(%class.HardwareSerial* %this) #1 align 2 {
entry:
  %this.addr = alloca %class.HardwareSerial*, align 2
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  br label %while.cond

while.cond:                                       ; preds = %while.body, %entry
  %_tx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %0 = load volatile i8, i8* %_tx_buffer_head, align 1
  %conv = zext i8 %0 to i16
  %_tx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %1 = load volatile i8, i8* %_tx_buffer_tail, align 1
  %conv2 = zext i8 %1 to i16
  %cmp = icmp ne i16 %conv, %conv2
  br i1 %cmp, label %while.body, label %while.end

while.body:                                       ; preds = %while.cond
  br label %while.cond

while.end:                                        ; preds = %while.cond
  %_ucsrb = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %2 = load i8*, i8** %_ucsrb, align 2
  %3 = ptrtoint i8* %2 to i16
  %4 = inttoptr i16 %3 to i8*
  %5 = load volatile i8, i8* %4, align 1
  %conv3 = zext i8 %5 to i16
  %and = and i16 %conv3, -17
  %conv4 = trunc i16 %and to i8
  store volatile i8 %conv4, i8* %4, align 1
  %_ucsrb5 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %6 = load i8*, i8** %_ucsrb5, align 2
  %7 = ptrtoint i8* %6 to i16
  %8 = inttoptr i16 %7 to i8*
  %9 = load volatile i8, i8* %8, align 1
  %conv6 = zext i8 %9 to i16
  %and7 = and i16 %conv6, -9
  %conv8 = trunc i16 %and7 to i8
  store volatile i8 %conv8, i8* %8, align 1
  %_ucsrb9 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %10 = load i8*, i8** %_ucsrb9, align 2
  %11 = ptrtoint i8* %10 to i16
  %12 = inttoptr i16 %11 to i8*
  %13 = load volatile i8, i8* %12, align 1
  %conv10 = zext i8 %13 to i16
  %and11 = and i16 %conv10, -129
  %conv12 = trunc i16 %and11 to i8
  store volatile i8 %conv12, i8* %12, align 1
  %_ucsrb13 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %14 = load i8*, i8** %_ucsrb13, align 2
  %15 = ptrtoint i8* %14 to i16
  %16 = inttoptr i16 %15 to i8*
  %17 = load volatile i8, i8* %16, align 1
  %conv14 = zext i8 %17 to i16
  %and15 = and i16 %conv14, -33
  %conv16 = trunc i16 %and15 to i8
  store volatile i8 %conv16, i8* %16, align 1
  %_rx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %18 = load volatile i8, i8* %_rx_buffer_tail, align 1
  %_rx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 8
  store volatile i8 %18, i8* %_rx_buffer_head, align 1
  ret void
}

; Function Attrs: nounwind
define i16 @_ZN14HardwareSerial9availableEv(%class.HardwareSerial* %this) unnamed_addr #1 align 2 {
entry:
  %this.addr = alloca %class.HardwareSerial*, align 2
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_rx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 8
  %0 = load volatile i8, i8* %_rx_buffer_head, align 1
  %conv = zext i8 %0 to i16
  %add = add nsw i16 64, %conv
  %_rx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %1 = load volatile i8, i8* %_rx_buffer_tail, align 1
  %conv2 = zext i8 %1 to i16
  %sub = sub nsw i16 %add, %conv2
  %rem = urem i16 %sub, 64
  ret i16 %rem
}

; Function Attrs: nounwind
define i16 @_ZN14HardwareSerial4peekEv(%class.HardwareSerial* %this) unnamed_addr #1 align 2 {
entry:
  %retval = alloca i16, align 2
  %this.addr = alloca %class.HardwareSerial*, align 2
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_rx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 8
  %0 = load volatile i8, i8* %_rx_buffer_head, align 1
  %conv = zext i8 %0 to i16
  %_rx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %1 = load volatile i8, i8* %_rx_buffer_tail, align 1
  %conv2 = zext i8 %1 to i16
  %cmp = icmp eq i16 %conv, %conv2
  br i1 %cmp, label %if.then, label %if.else

if.then:                                          ; preds = %entry
  store i16 -1, i16* %retval
  br label %return

if.else:                                          ; preds = %entry
  %_rx_buffer_tail3 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %2 = load volatile i8, i8* %_rx_buffer_tail3, align 1
  %idxprom = zext i8 %2 to i16
  %_rx_buffer = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 12
  %arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* %_rx_buffer, i32 0, i16 %idxprom
  %3 = load i8, i8* %arrayidx, align 1
  %conv4 = zext i8 %3 to i16
  store i16 %conv4, i16* %retval
  br label %return

return:                                           ; preds = %if.else, %if.then
  %4 = load i16, i16* %retval
  ret i16 %4
}

; Function Attrs: nounwind
define i16 @_ZN14HardwareSerial4readEv(%class.HardwareSerial* %this) unnamed_addr #1 align 2 {
entry:
  %retval = alloca i16, align 2
  %this.addr = alloca %class.HardwareSerial*, align 2
  %c = alloca i8, align 1
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_rx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 8
  %0 = load volatile i8, i8* %_rx_buffer_head, align 1
  %conv = zext i8 %0 to i16
  %_rx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %1 = load volatile i8, i8* %_rx_buffer_tail, align 1
  %conv2 = zext i8 %1 to i16
  %cmp = icmp eq i16 %conv, %conv2
  br i1 %cmp, label %if.then, label %if.else

if.then:                                          ; preds = %entry
  store i16 -1, i16* %retval
  br label %return

if.else:                                          ; preds = %entry
  %_rx_buffer_tail3 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %2 = load volatile i8, i8* %_rx_buffer_tail3, align 1
  %idxprom = zext i8 %2 to i16
  %_rx_buffer = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 12
  %arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* %_rx_buffer, i32 0, i16 %idxprom
  %3 = load i8, i8* %arrayidx, align 1
  store i8 %3, i8* %c, align 1
  %_rx_buffer_tail4 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  %4 = load volatile i8, i8* %_rx_buffer_tail4, align 1
  %conv5 = zext i8 %4 to i16
  %add = add nsw i16 %conv5, 1
  %conv6 = trunc i16 %add to i8
  %conv7 = zext i8 %conv6 to i16
  %rem = srem i16 %conv7, 64
  %conv8 = trunc i16 %rem to i8
  %_rx_buffer_tail9 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 9
  store volatile i8 %conv8, i8* %_rx_buffer_tail9, align 1
  %5 = load i8, i8* %c, align 1
  %conv10 = zext i8 %5 to i16
  store i16 %conv10, i16* %retval
  br label %return

return:                                           ; preds = %if.else, %if.then
  %6 = load i16, i16* %retval
  ret i16 %6
}

; Function Attrs: nounwind
define i16 @_ZN14HardwareSerial17availableForWriteEv(%class.HardwareSerial* %this) #1 align 2 {
entry:
  %retval = alloca i16, align 2
  %this.addr = alloca %class.HardwareSerial*, align 2
  %head = alloca i8, align 1
  %tail = alloca i8, align 1
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_tx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %0 = load volatile i8, i8* %_tx_buffer_head, align 1
  store i8 %0, i8* %head, align 1
  %_tx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %1 = load volatile i8, i8* %_tx_buffer_tail, align 1
  store i8 %1, i8* %tail, align 1
  %2 = load i8, i8* %head, align 1
  %conv = zext i8 %2 to i16
  %3 = load i8, i8* %tail, align 1
  %conv2 = zext i8 %3 to i16
  %cmp = icmp sge i16 %conv, %conv2
  br i1 %cmp, label %if.then, label %if.end

if.then:                                          ; preds = %entry
  %4 = load i8, i8* %head, align 1
  %conv3 = zext i8 %4 to i16
  %sub = sub nsw i16 63, %conv3
  %5 = load i8, i8* %tail, align 1
  %conv4 = zext i8 %5 to i16
  %add = add nsw i16 %sub, %conv4
  store i16 %add, i16* %retval
  br label %return

if.end:                                           ; preds = %entry
  %6 = load i8, i8* %tail, align 1
  %conv5 = zext i8 %6 to i16
  %7 = load i8, i8* %head, align 1
  %conv6 = zext i8 %7 to i16
  %sub7 = sub nsw i16 %conv5, %conv6
  %sub8 = sub nsw i16 %sub7, 1
  store i16 %sub8, i16* %retval
  br label %return

return:                                           ; preds = %if.end, %if.then
  %8 = load i16, i16* %retval
  ret i16 %8
}

; Function Attrs: nounwind
define void @_ZN14HardwareSerial5flushEv(%class.HardwareSerial* %this) unnamed_addr #1 align 2 {
entry:
  %this.addr = alloca %class.HardwareSerial*, align 2
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_written = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 7
  %0 = load i8, i8* %_written, align 1
  %tobool = trunc i8 %0 to i1
  br i1 %tobool, label %if.end, label %if.then

if.then:                                          ; preds = %entry
  br label %while.end

if.end:                                           ; preds = %entry
  br label %while.cond

while.cond:                                       ; preds = %if.end.20, %if.end
  %_ucsrb = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %1 = load i8*, i8** %_ucsrb, align 2
  %2 = ptrtoint i8* %1 to i16
  %3 = inttoptr i16 %2 to i8*
  %4 = load volatile i8, i8* %3, align 1
  %conv = zext i8 %4 to i16
  %and = and i16 %conv, 32
  %tobool2 = icmp ne i16 %and, 0
  br i1 %tobool2, label %lor.end, label %lor.rhs

lor.rhs:                                          ; preds = %while.cond
  %_ucsra = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %5 = load i8*, i8** %_ucsra, align 2
  %6 = ptrtoint i8* %5 to i16
  %7 = inttoptr i16 %6 to i8*
  %8 = load volatile i8, i8* %7, align 1
  %conv3 = zext i8 %8 to i16
  %and4 = and i16 %conv3, 64
  %tobool5 = icmp ne i16 %and4, 0
  %lnot = xor i1 %tobool5, true
  br label %lor.end

lor.end:                                          ; preds = %lor.rhs, %while.cond
  %9 = phi i1 [ true, %while.cond ], [ %lnot, %lor.rhs ]
  br i1 %9, label %while.body, label %while.end

while.body:                                       ; preds = %lor.end
  %10 = load volatile i8, i8* inttoptr (i16 95 to i8*), align 1
  %conv6 = zext i8 %10 to i16
  %and7 = and i16 %conv6, 128
  %tobool8 = icmp ne i16 %and7, 0
  br i1 %tobool8, label %if.end.20, label %land.lhs.true

land.lhs.true:                                    ; preds = %while.body
  %_ucsrb9 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %11 = load i8*, i8** %_ucsrb9, align 2
  %12 = ptrtoint i8* %11 to i16
  %13 = inttoptr i16 %12 to i8*
  %14 = load volatile i8, i8* %13, align 1
  %conv10 = zext i8 %14 to i16
  %and11 = and i16 %conv10, 32
  %tobool12 = icmp ne i16 %and11, 0
  br i1 %tobool12, label %if.then.13, label %if.end.20

if.then.13:                                       ; preds = %land.lhs.true
  %_ucsra14 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %15 = load i8*, i8** %_ucsra14, align 2
  %16 = ptrtoint i8* %15 to i16
  %17 = inttoptr i16 %16 to i8*
  %18 = load volatile i8, i8* %17, align 1
  %conv15 = zext i8 %18 to i16
  %and16 = and i16 %conv15, 32
  %tobool17 = icmp ne i16 %and16, 0
  br i1 %tobool17, label %if.then.18, label %if.end.19

if.then.18:                                       ; preds = %if.then.13
  call void @_ZN14HardwareSerial17_tx_udr_empty_irqEv(%class.HardwareSerial* %this1)
  br label %if.end.19

if.end.19:                                        ; preds = %if.then.18, %if.then.13
  br label %if.end.20

if.end.20:                                        ; preds = %if.end.19, %land.lhs.true, %while.body
  br label %while.cond

while.end:                                        ; preds = %if.then, %lor.end
  ret void
}

; Function Attrs: nounwind
define i16 @_ZN14HardwareSerial5writeEh(%class.HardwareSerial* %this, i8 zeroext %c) unnamed_addr #1 align 2 {
entry:
  %retval = alloca i16, align 2
  %this.addr = alloca %class.HardwareSerial*, align 2
  %c.addr = alloca i8, align 1
  %i = alloca i8, align 1
  store %class.HardwareSerial* %this, %class.HardwareSerial** %this.addr, align 2
  store i8 %c, i8* %c.addr, align 1
  %this1 = load %class.HardwareSerial*, %class.HardwareSerial** %this.addr
  %_tx_buffer_head = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %0 = load volatile i8, i8* %_tx_buffer_head, align 1
  %conv = zext i8 %0 to i16
  %_tx_buffer_tail = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %1 = load volatile i8, i8* %_tx_buffer_tail, align 1
  %conv2 = zext i8 %1 to i16
  %cmp = icmp eq i16 %conv, %conv2
  br i1 %cmp, label %land.lhs.true, label %if.end

land.lhs.true:                                    ; preds = %entry
  %_ucsra = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %2 = load i8*, i8** %_ucsra, align 2
  %3 = ptrtoint i8* %2 to i16
  %4 = inttoptr i16 %3 to i8*
  %5 = load volatile i8, i8* %4, align 1
  %conv3 = zext i8 %5 to i16
  %and = and i16 %conv3, 32
  %tobool = icmp ne i16 %and, 0
  br i1 %tobool, label %if.then, label %if.end

if.then:                                          ; preds = %land.lhs.true
  %6 = load i8, i8* %c.addr, align 1
  %_udr = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 6
  %7 = load i8*, i8** %_udr, align 2
  store volatile i8 %6, i8* %7, align 1
  %_ucsra4 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %8 = load i8*, i8** %_ucsra4, align 2
  %9 = ptrtoint i8* %8 to i16
  %10 = inttoptr i16 %9 to i8*
  %11 = load volatile i8, i8* %10, align 1
  %conv5 = zext i8 %11 to i16
  %or = or i16 %conv5, 64
  %conv6 = trunc i16 %or to i8
  store volatile i8 %conv6, i8* %10, align 1
  store i16 1, i16* %retval
  br label %return

if.end:                                           ; preds = %land.lhs.true, %entry
  %_tx_buffer_head7 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %12 = load volatile i8, i8* %_tx_buffer_head7, align 1
  %conv8 = zext i8 %12 to i16
  %add = add nsw i16 %conv8, 1
  %rem = srem i16 %add, 64
  %conv9 = trunc i16 %rem to i8
  store i8 %conv9, i8* %i, align 1
  br label %while.cond

while.cond:                                       ; preds = %if.end.24, %if.end
  %13 = load i8, i8* %i, align 1
  %conv10 = zext i8 %13 to i16
  %_tx_buffer_tail11 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 11
  %14 = load volatile i8, i8* %_tx_buffer_tail11, align 1
  %conv12 = zext i8 %14 to i16
  %cmp13 = icmp eq i16 %conv10, %conv12
  br i1 %cmp13, label %while.body, label %while.end

while.body:                                       ; preds = %while.cond
  %15 = load volatile i8, i8* inttoptr (i16 95 to i8*), align 1
  %conv14 = zext i8 %15 to i16
  %and15 = and i16 %conv14, 128
  %tobool16 = icmp ne i16 %and15, 0
  br i1 %tobool16, label %if.else, label %if.then.17

if.then.17:                                       ; preds = %while.body
  %_ucsra18 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 3
  %16 = load i8*, i8** %_ucsra18, align 2
  %17 = ptrtoint i8* %16 to i16
  %18 = inttoptr i16 %17 to i8*
  %19 = load volatile i8, i8* %18, align 1
  %conv19 = zext i8 %19 to i16
  %and20 = and i16 %conv19, 32
  %tobool21 = icmp ne i16 %and20, 0
  br i1 %tobool21, label %if.then.22, label %if.end.23

if.then.22:                                       ; preds = %if.then.17
  call void @_ZN14HardwareSerial17_tx_udr_empty_irqEv(%class.HardwareSerial* %this1)
  br label %if.end.23

if.end.23:                                        ; preds = %if.then.22, %if.then.17
  br label %if.end.24

if.else:                                          ; preds = %while.body
  br label %if.end.24

if.end.24:                                        ; preds = %if.else, %if.end.23
  br label %while.cond

while.end:                                        ; preds = %while.cond
  %20 = load i8, i8* %c.addr, align 1
  %_tx_buffer_head25 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  %21 = load volatile i8, i8* %_tx_buffer_head25, align 1
  %idxprom = zext i8 %21 to i16
  %_tx_buffer = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 13
  %arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* %_tx_buffer, i32 0, i16 %idxprom
  store i8 %20, i8* %arrayidx, align 1
  %22 = load i8, i8* %i, align 1
  %_tx_buffer_head26 = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 10
  store volatile i8 %22, i8* %_tx_buffer_head26, align 1
  %_ucsrb = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 4
  %23 = load i8*, i8** %_ucsrb, align 2
  %24 = ptrtoint i8* %23 to i16
  %25 = inttoptr i16 %24 to i8*
  %26 = load volatile i8, i8* %25, align 1
  %conv27 = zext i8 %26 to i16
  %or28 = or i16 %conv27, 32
  %conv29 = trunc i16 %or28 to i8
  store volatile i8 %conv29, i8* %25, align 1
  %_written = getelementptr inbounds %class.HardwareSerial, %class.HardwareSerial* %this1, i32 0, i32 7
  store i8 1, i8* %_written, align 1
  store i16 1, i16* %retval
  br label %return

return:                                           ; preds = %while.end, %if.then
  %27 = load i16, i16* %retval
  ret i16 %27
}

declare i16 @_ZN5Print5writeEPKhj(%class.Print*, i8*, i16) #0

attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" }

!llvm.ident = !{!0}

!0 = !{!"clang version 3.8.0 (https://github.com/avr-llvm/clang.git bc1779778787f8cfca43849f8a4412b5ca7432c1) (llvm/llvm.git 693f1d90faf67af7ca0ec14e3eb8643ac4a1972f)"}

[dylanmckay]

LLVM commit 693f1d9 is two weeks old now :)

If you pull the latest changes and run clang again, it will most likely print

you have reached a bug - division/modulus greater than 16-bits is broken - see GitHub issue #149

If it doesn't, then this is a different problem.

I have a fix in the works which will allow us the get rid of almost all of our pseudo instructions and also fix issue #149. I am intending on getting it upstreamed to LLVM trunk however, so it could take a little while.

[4ntoine]

ok, great. I'm going to pull, recompile and test the latest revision

[dylanmckay]

I just checked by running the IR through llc - this is a duplicate of #149.

Closing this issue, discussion can be moved to #149.

[agnat]

I have a fix in the works which will allow us the get rid of almost all of our pseudo instructions [...]

Awesome. Why isn't there a PR for this? I wanna watch... :-D

[4ntoine]

i've just checked out the latest revision and i'm still having crash (but with "you have reached a bug - division/modulus greater than 16-bits is broken - see GitHub issue #149" output as expected):

MBA-Anton:bin asmirnov$ ./clang --version
clang version 3.8.0 (https://github.com/avr-llvm/clang.git bc1779778787f8cfca43849f8a4412b5ca7432c1) (llvm/llvm.git c4c1b5f054a5fb93668b4f1780a8b6b72fc27147)
Target: x86_64-apple-darwin14.3.0
Thread model: posix

Just note, no actions required

[dylanmckay]

Awesome. Why isn't there a PR for this? I wanna watch... :-D

It's not very progressed, but I've recently got the idea fleshed out :)

A new LegalizeAction will be added, named Split. This will be the same as LegalizeAction::Expand except that it will always expand by splitting (which will remove all assumptions about pointer size and legal types).

I messaged llvm-dev. Several backends seem to have hit the same problem we have. Notably, this fix would remove some code duplication in the AMDGPU backend. The post did not get many replies (sadly), so I am not sure if this change would be welcomed into trunk.

The infrastructure is already there - I just need to refactor it.

[agnat]

Sounds good.

so I am not sure if this change would be welcomed into trunk.

Yeah, it seems a bit ... difficult to get things landed. Even simple fixes are hard to get in until you have a certain track record. But that's just how it is.

One thing they recommend is to start reviewing patches of others. But I don't feel qualified to comment on any functional issue. All I can do is look for general coding/design issues, which feels a bit thin.

No matter what it looks like now, consider putting it in a PR anyway. It is not embarrassing. It's actually quite fun to have a PR to chat over the code. Cathedrals vs. Bazaars &c... Just think about it ;)