LLVM ERROR: Cannot select — umul_lohi not implemented

[shepmaster]

LLVM ERROR: Cannot select: t35: i8 = mulhs t2, t4
  t2: i8,ch = CopyFromReg t0, Register:i8 %vreg27
    t1: i8 = Register %vreg27
  t4: i8,ch = CopyFromReg t0, Register:i8 %vreg25
    t3: i8 = Register %vreg25
In function: _ZN3num14from_str_radix20h7837196669301488416E

More information is available in the original issue. I'll let @dylanmckay copy over whatever information is important.

[shepmaster]

Compiled with llc -march=avr -mcpu=atmega328p -filetype=obj all-core.ll:

; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8"
target triple = "avr-atmel-none"

; Function Attrs: nounwind readnone
declare i16 @llvm.bswap.i16(i16) #1

; Function Attrs: nounwind readnone uwtable
define i16 @_ZN3num6bignum10u8.FullOps8full_mul20h0abbd05633bc14b3GhgE(i8, i8, i8) unnamed_addr #3 {
entry-block:
  %3 = zext i8 %2 to i16
  %4 = add i16 0, %3
  %sret_slot.sroa.0.0.insert.insert = tail call i16 @llvm.bswap.i16(i16 %4)
  ret i16 %sret_slot.sroa.0.0.insert.insert
}

[dylanmckay]

Test case added in test/CodeGen/AVR/issue-cannot-select-mulhs.ll at bf5a68a.

[shepmaster]

Note that the error for the reduced case is:

LLVM ERROR: Cannot select: t9: i16 = bswap t7
  t7: i16 = zero_extend t6
    t6: i8,ch = CopyFromReg t0, Register:i8 %vreg2
      t5: i8 = Register %vreg2

Perhaps that's a separate bug or it explains when you said "we currently do support multiplication"?

[shepmaster]

Popping into the debugger, I see that SelectionDAGISel::DoInstructionSelection is calling Select with a node with opcode 219. I believe that to be a NodeType::RET_FLAG. SelectionDAGISel::SelectCodeCommon doesn't know how to handle that, so it asserts.

[shepmaster]

with opcode 219

That's from the wrong iteration. I think the real culprit is 103 (BSWAP), which seems suspiciously specific. I'm going to try re-bugpointing with an even more specific test.

[shepmaster]

If I constrain the issue to the original mulhs, I reduce to this:

; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8"
target triple = "avr-atmel-none"

define fastcc void @from_str_radix(i32) unnamed_addr {
entry-block:
  br i1 undef, label %return, label %next

next:                                             ; preds = %entry-block
  %1 = trunc i32 %0 to i8
  br label %exit

exit:                                             ; preds = %match_case1, %next
  %result.0282 = phi i8 [ %5, %match_case1 ], [ 0, %next ]
  %2 = icmp ult i32 undef, %0
  br i1 %2, label %match_case0, label %return

match_case0:                                      ; preds = %exit
  %3 = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %result.0282, i8 %1)
  %4 = extractvalue { i8, i1 } %3, 1
  %brmerge = or i1 %4, undef
  br i1 %brmerge, label %return, label %match_case1

match_case1:                                      ; preds = %match_case0
  %5 = extractvalue { i8, i1 } undef, 0
  br label %exit

return:                                           ; preds = %match_case0, %exit, %entry-block
  ret void
}

; Function Attrs: nounwind readnone
declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8) #0

attributes #0 = { nounwind readnone }

[shepmaster]

Repeating the same debugging as before, the offending opcode is 90, MULHS.

FWIW, the backtrace at the interesting point is

llvm::SelectionDAGISel::CannotYetSelect(this=..., N=...) at SelectionDAGISel.cpp:3417
llvm::SelectionDAGISel::SelectCodeCommon(this=..., NodeToMatch=..., MatcherTable="\x16Ny", TableSize=2485) at SelectionDAGISel.cpp:3368
llvm::AVRDAGToDAGISel::SelectCode(this=..., N=...) at AVRGenDAGISel.inc:1309
llvm::AVRDAGToDAGISel::Select(this=..., N=...) at AVRISelDAGToDAG.cpp:544
llvm::SelectionDAGISel::DoInstructionSelection(this=...) at SelectionDAGISel.cpp:940
llvm::SelectionDAGISel::CodeGenAndEmitDAG(this=...) at SelectionDAGISel.cpp:840
llvm::SelectionDAGISel::SelectBasicBlock(this=..., Begin=llvm::BasicBlock::const_iterator @ ..., End=llvm::BasicBlock::const_iterator @ ..., HadTailCall=...) at SelectionDAGISel.cpp:668
llvm::SelectionDAGISel::SelectAllBasicBlocks(this=..., Fn=...) at SelectionDAGISel.cpp:1359

[dylanmckay]

From memory, you can pass -debug-only=isel to llc to trace the ISel selection process. Can you try this to figure out the sequence of operations it took to map (presumably a mul) into mulhs?.

[shepmaster]

trace the ISel selection process

Ah, that's how you enable those debug prints. I hadn't dug into that yet. Here are the full results (577 lines). It ends with:

ISEL: Starting pattern match on root node: t25: i8 = mulhs t2, t4

  Initial Opcode index to 0
  Match failed at index 0
LLVM ERROR: Cannot select: t25: i8 = mulhs t2, t4
  t2: i8,ch = CopyFromReg t0, Register:i8 %vreg1
    t1: i8 = Register %vreg1
  t4: i8,ch = CopyFromReg t0, Register:i8 %vreg0
    t3: i8 = Register %vreg0
In function: from_str_radix

[shepmaster]

Note that the lines like Truncating 16 to 16 are from my own hack to work around another assertion in APInt:

commit 508ab43fd226303dd9e58576060bde576f05a2a3
Author: Jake Goulding <jake.goulding@gmail.com>
Date:   Thu Jan 14 12:15:20 2016 -0500

    [HACK] Avoid truncate, zero-, sign-extending 16-to-16

diff --git a/lib/Support/APInt.cpp b/lib/Support/APInt.cpp
index 23f89bb..f0706c1 100644
--- a/lib/Support/APInt.cpp
+++ b/lib/Support/APInt.cpp
@@ -930,6 +930,10 @@ double APInt::roundToDouble(bool isSigned) const {

 // Truncate to new width.
 APInt APInt::trunc(unsigned width) const {
+  if (width == BitWidth) {
+    fprintf(stderr, "Truncating %d to %d\n", BitWidth, width);
+    return *this;
+  }
   assert(width < BitWidth && "Invalid APInt Truncate request");
   assert(width && "Can't truncate to 0 bits");

@@ -953,6 +957,11 @@ APInt APInt::trunc(unsigned width) const {

 // Sign extend to a new width.
 APInt APInt::sext(unsigned width) const {
+  if (width == BitWidth) {
+    fprintf(stderr, "Sign extending %d to %d\n", BitWidth, width);
+    return *this;
+  }
+
   assert(width > BitWidth && "Invalid APInt SignExtend request");

   if (width <= APINT_BITS_PER_WORD) {
@@ -994,6 +1003,11 @@ APInt APInt::sext(unsigned width) const {

 //  Zero extend to a new width.
 APInt APInt::zext(unsigned width) const {
+  if (width == BitWidth) {
+    fprintf(stderr, "Zero extending %d to %d\n", BitWidth, width);
+    return *this;
+  }
+
   assert(width > BitWidth && "Invalid APInt ZeroExtend request");

   if (width <= APINT_BITS_PER_WORD)

[shepmaster]

And the bswap isel trace, for good measure.