[AVR] Factor out mayLoad in tablegen patterns

Patch by Gergo Erdi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314897 91177308-0d34-0410-b5e6-96231b3b80d8

Author: gergoerdi

lib/Target/AVR/AVRInstrInfo.td

@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
 // Load program memory operations.
 let canFoldAsLoad = 1,
 isReMaterializable = 1,
+mayLoad = 1,
 hasSideEffects = 0 in
 {
   let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
                Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
-  let mayLoad = 1,
-  Defs = [R31R30] in
+  let Defs = [R31R30] in
   {
     def LPMRdZPi : FLPMX<0,
                          1,