Final continuation jump missing from MBB #49

gergoerdi · 2017-05-10T04:22:49Z

Here's the minimized LLVM IR:

target triple = "avr-atmel-none"

define internal fastcc void @loopy() unnamed_addr{
start:
  br label %bb7.preheader

bb7.preheader:                                    ; preds = %bb10, %start
  %i = phi i8 [ 0, %start ], [ %j, %bb10 ]
  %j = phi i8 [ 1, %start ], [ %next, %bb10 ]
  br label %bb10

bb4:                                              ; preds = %bb10
  ret void

bb10:                                             ; preds = %bb7.preheader
  tail call fastcc void @observe(i8 %i, i8 1)
  %0 = icmp ult i8 %j, 20
  %1 = zext i1 %0 to i8
  %next = add i8 %j, %1
  br i1 %0, label %bb7.preheader, label %bb4

}

declare void @observe(i8, i8) unnamed_addr;

And here's the generated assembly:

loopy:                                  ; @loopy
; BB#0:                                 ; %start
        push    r16
        push    r17
        ldi     r17, 1
        ldi     r24, 0
LBB0_1:                                 ; %bb4
        pop     r17
        pop     r16
        ret
LBB0_2:                                 ; %bb10
        ldi     r17, 0
LBB0_3:                                 ; %bb10
        add     r17, r16
        cpi     r16, 20
        mov     r24, r16
        brlo    .+2
        rjmp    LBB0_1
; BB#4:                                 ; %bb7.preheader
        mov     r16, r17
        ldi     r17, 1
        ldi     r22, 1
        call    observe
        cpi     r16, 20
        brlo    .+2
        rjmp    LBB0_2
        rjmp    LBB0_3

The problem is that BB#0 doesn't jump to its continuation, and so falls through to LBB0_1 which should only happen at the end of the loop.

The text was updated successfully, but these errors were encountered:

gergoerdi · 2017-05-10T04:49:58Z

This is actually similar to #46. The selection DAG for loopy:start with -O1 doesn't have the final jump:

Initial selection DAG: BB#0 'loopy:start'
SelectionDAG has 8 nodes:
  t0: ch = EntryToken
    t3: ch = CopyToReg t0, Register:i8 %vreg3, Constant:i8<0>
    t6: ch = CopyToReg t0, Register:i8 %vreg4, Constant:i8<1>
  t7: ch = TokenFactor t3, t6

but the final jump is present with -O0:

Initial selection DAG: BB#0 'loopy:start'
SelectionDAG has 10 nodes:
  t0: ch = EntryToken
      t3: ch = CopyToReg t0, Register:i8 %vreg3, Constant:i8<0>
      t6: ch = CopyToReg t0, Register:i8 %vreg4, Constant:i8<1>
    t8: ch = TokenFactor t3, t6
  t9: ch = br t8, BasicBlock:ch<bb7.preheader 0x2f1f9a8>

Could it be that this is all fine & dandy, the fall-through is intentional (and so the fix from #46 is not needed), and the real problem is that EmitInstrWithCustomInserter screws up the MBB ordering?

gergoerdi · 2017-05-10T05:45:21Z

I think the problem is indeed that EmitInstrWithCustomInserter inserts trueMBB and falseMBB to MF's start instead of maintaining MBB's position.

I'll experiment with replacing

 MachineFunction::iterator I = MBB->getParent()->begin();
 ++I;
 MF->insert(I, trueMBB);
 MF->insert(I, falseMBB);

with

  MachineFunction::iterator I;
  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
  MF->insert(I, trueMBB);
  MF->insert(I, falseMBB);

gergoerdi · 2017-05-10T06:32:57Z

The change described in #49 (comment) fixes the original issue, but breaks other code spectacularly; in particular, given the following LLVM IR:

source_filename = "libcore_mini.cgu-0.rs"
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8"
target triple = "avr-atmel-none"

%"option::Option<u32>" = type { i32, [0 x i32], [1 x i32] }

define void @pow(%"option::Option<u32>"* noalias nocapture sret dereferenceable(8), i32) unnamed_addr {
start:
  %v3 = tail call i32 @llvm.ctlz.i32(i32 %1, i1 false)
  %v4 = trunc i32 %v3 to i8
  %v7 = shl i8 1, %v4
  %v8 = zext i8 %v7 to i32
  %v9 = getelementptr inbounds %"option::Option<u32>", %"option::Option<u32>"* %0, i16 0, i32 0
  store i32 1, i32* %v9, align 4
  %v10 = getelementptr inbounds %"option::Option<u32>", %"option::Option<u32>"* %0, i16 0, i32 2, i16 0
  store i32 %v8, i32* %v10, align 4
  ret void
}

declare i32 @llvm.ctlz.i32(i32, i1)

compiling it to AVR crashes with

#0 0x00000000017210d5 llvm::sys::PrintStackTrace(llvm::raw_ostream&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x17210d5)
#1 0x000000000171f0ee llvm::sys::RunSignalHandlers() (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x171f0ee)
#2 0x000000000171f252 SignalHandler(int) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x171f252)
#3 0x00007f25e76e3330 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)
#4 0x00000000010a2b55 llvm::LiveVariables::runOnBlock(llvm::MachineBasicBlock*, unsigned int) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x10a2b55)
#5 0x00000000010a357d llvm::LiveVariables::runOnMachineFunction(llvm::MachineFunction&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x10a357d)
#6 0x00000000010e8573 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x10e8573)
#7 0x000000000138ba53 llvm::FPPassManager::runOnFunction(llvm::Function&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x138ba53)
#8 0x000000000138bafc llvm::FPPassManager::runOnModule(llvm::Module&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x138bafc)
#9 0x000000000138c85f llvm::legacy::PassManagerImpl::run(llvm::Module&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x138c85f)
#10 0x0000000000697f74 compileModule(char**, llvm::LLVMContext&) (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x697f74)
#11 0x0000000000646a90 main (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x646a90)
#12 0x00007f25e688af45 __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x21f45)
#13 0x000000000068d2b5 _start (/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc+0x68d2b5)
Stack dump:
0.	Program arguments: /home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/bin/llc --mcpu=atmega328p a.ll --debug 
1.	Running pass 'Function Pass Manager' on module 'a.ll'.
2.	Running pass 'Live Variable Analysis' on function '@pow'

gergoerdi · 2017-05-10T06:34:27Z

# Machine code for function pow: IsSSA, TracksLiveness
Function Live Ins: %R25R24 in %vreg0, %R21R20 in %vreg1, %R23R22 in %vreg2

0B	BB#1: derived from LLVM BB %start
	    Predecessors according to CFG: BB#0 BB#2
16B		%vreg131<def> = PHI %vreg69, <BB#0>, %vreg130, <BB#2>; DREGS:%vreg131,%vreg69 IWREGS:%vreg130
32B		%vreg132<def> = COPY %vreg131:sub_lo; GPR8:%vreg132 DREGS:%vreg131
48B		CPRdRr %vreg132, %R0, %SREG<imp-def>; GPR8:%vreg132
64B		BREQk <BB#4>, %SREG<imp-use>
	    Successors according to CFG: BB#3(?%) BB#4(?%)

80B	BB#3: derived from LLVM BB %start
	    Predecessors according to CFG: BB#1 BB#3
96B		%vreg138<def> = PHI %vreg44, <BB#1>, %vreg139, <BB#3>; GPR8:%vreg138,%vreg139 LD8:%vreg44
112B		%vreg136<def> = PHI %vreg132, <BB#1>, %vreg137, <BB#3>; LD8:%vreg136,%vreg137 GPR8:%vreg132
128B		%vreg139<def,tied1> = LSLRd %vreg138<tied0>, %SREG<imp-def>; GPR8:%vreg139,%vreg138
144B		%vreg137<def,tied1> = SUBIRdK %vreg136<tied0>, 1, %SREG<imp-def>; LD8:%vreg137,%vreg136
160B		BRNEk <BB#3>, %SREG<imp-use>
	    Successors according to CFG: BB#4(?%) BB#3(?%)

176B	BB#4: derived from LLVM BB %start
	    Predecessors according to CFG: BB#1 BB#3
192B		%vreg133<def> = PHI %vreg44, <BB#1>, %vreg139, <BB#3>; GPR8:%vreg133,%vreg139 LD8:%vreg44
208B		%vreg134<def> = ZEXT %vreg133<kill>, %SREG<imp-def,dead>; DREGS:%vreg134 GPR8:%vreg133
224B		%vreg135<def> = COPY %vreg0; PTRDISPREGS:%vreg135 DREGS:%vreg0
240B		STDWPtrQRr %vreg135, 4, %vreg134<kill>; mem:ST2[%v10](align=4) PTRDISPREGS:%vreg135 DREGS:%vreg134
256B		RET

272B	BB#2: derived from LLVM BB %start
	    Predecessors according to CFG: BB#0
288B		RJMPk <BB#1>
	    Successors according to CFG: BB#1(?%)

304B	BB#0: derived from LLVM BB %start
	    Live Ins: %R25R24 %R21R20 %R23R22
320B		%vreg2<def> = COPY %R23R22; DREGS:%vreg2
336B		%vreg1<def> = COPY %R21R20; DREGS:%vreg1
352B		%vreg0<def> = COPY %R25R24; DREGS:%vreg0
368B		%vreg3<def> = LDIWRdK 1; DLDREGS:%vreg3
384B		%vreg5<def> = COPY %vreg0; PTRREGS:%vreg5 DREGS:%vreg0
400B		%vreg4<earlyclobber,def,tied1> = STWPtrPiRr %vreg5<tied0>, %vreg3<kill>, 2; mem:ST2[%v91](align=4) PTRREGS:%vreg4,%vreg5 DLDREGS:%vreg3
416B		%vreg6<def> = LDIWRdK 0; DLDREGS:%vreg6
432B		%vreg7<def> = COPY %vreg4; PTRDISPREGS:%vreg7 PTRREGS:%vreg4
448B		STWPtrRr %vreg7<kill>, %vreg6; mem:ST2[%v91+2] PTRDISPREGS:%vreg7 DLDREGS:%vreg6
464B		%vreg8<def> = COPY %vreg0; PTRDISPREGS:%vreg8 DREGS:%vreg0
480B		STDWPtrQRr %vreg8, 6, %vreg6; mem:ST2[%v10+2] PTRDISPREGS:%vreg8 DLDREGS:%vreg6
496B		%vreg9<def,tied1> = LSRWRd %vreg2<tied0>, %SREG<imp-def,dead>; DREGS:%vreg9,%vreg2
512B		%vreg10<def,tied1> = ORWRdRr %vreg2<tied0>, %vreg9<kill>, %SREG<imp-def,dead>; DREGS:%vreg10,%vreg2,%vreg9
528B		%vreg11<def,tied1> = LSRWRd %vreg10<tied0>, %SREG<imp-def,dead>; DREGS:%vreg11,%vreg10
544B		%vreg12<def,tied1> = LSRWRd %vreg11<tied0>, %SREG<imp-def,dead>; DREGS:%vreg12,%vreg11
560B		%vreg13<def,tied1> = ORWRdRr %vreg10<tied0>, %vreg12<kill>, %SREG<imp-def,dead>; DREGS:%vreg13,%vreg10,%vreg12
576B		%vreg14<def,tied1> = LSRWRd %vreg13<tied0>, %SREG<imp-def,dead>; DREGS:%vreg14,%vreg13
592B		%vreg15<def,tied1> = LSRWRd %vreg14<tied0>, %SREG<imp-def,dead>; DREGS:%vreg15,%vreg14
608B		%vreg16<def,tied1> = LSRWRd %vreg15<tied0>, %SREG<imp-def,dead>; DREGS:%vreg16,%vreg15
624B		%vreg17<def,tied1> = LSRWRd %vreg16<tied0>, %SREG<imp-def,dead>; DREGS:%vreg17,%vreg16
640B		%vreg18<def,tied1> = ORWRdRr %vreg13<tied0>, %vreg17<kill>, %SREG<imp-def,dead>; DREGS:%vreg18,%vreg13,%vreg17
656B		%vreg19<def,tied1> = LSRWRd %vreg18<tied0>, %SREG<imp-def,dead>; DREGS:%vreg19,%vreg18
672B		%vreg20<def,tied1> = LSRWRd %vreg19<tied0>, %SREG<imp-def,dead>; DREGS:%vreg20,%vreg19
688B		%vreg21<def,tied1> = LSRWRd %vreg20<tied0>, %SREG<imp-def,dead>; DREGS:%vreg21,%vreg20
704B		%vreg22<def,tied1> = LSRWRd %vreg21<tied0>, %SREG<imp-def,dead>; DREGS:%vreg22,%vreg21
720B		%vreg23<def,tied1> = LSRWRd %vreg22<tied0>, %SREG<imp-def,dead>; DREGS:%vreg23,%vreg22
736B		%vreg24<def,tied1> = LSRWRd %vreg23<tied0>, %SREG<imp-def,dead>; DREGS:%vreg24,%vreg23
752B		%vreg25<def,tied1> = LSRWRd %vreg24<tied0>, %SREG<imp-def,dead>; DREGS:%vreg25,%vreg24
768B		%vreg26<def,tied1> = LSRWRd %vreg25<tied0>, %SREG<imp-def,dead>; DREGS:%vreg26,%vreg25
784B		%vreg27<def,tied1> = ORWRdRr %vreg18<tied0>, %vreg26<kill>, %SREG<imp-def,dead>; DREGS:%vreg27,%vreg18,%vreg26
800B		%vreg28<def,tied1> = COMWRd %vreg27<tied0>, %SREG<imp-def,dead>; DREGS:%vreg28,%vreg27
816B		%vreg29<def,tied1> = LSRWRd %vreg28<tied0>, %SREG<imp-def,dead>; DLDREGS:%vreg29 DREGS:%vreg28
832B		%vreg30<def,tied1> = ANDIWRdK %vreg29<tied0>, 21845, %SREG<imp-def,dead>; DLDREGS:%vreg30,%vreg29
848B		%vreg31<def,tied1> = SUBWRdRr %vreg28<tied0>, %vreg30<kill>, %SREG<imp-def,dead>; DLDREGS:%vreg31,%vreg30 DREGS:%vreg28
864B		%vreg32<def,tied1> = ANDIWRdK %vreg31<tied0>, 13107, %SREG<imp-def,dead>; DLDREGS:%vreg32,%vreg31
880B		%vreg33<def,tied1> = LSRWRd %vreg31<tied0>, %SREG<imp-def,dead>; DREGS:%vreg33 DLDREGS:%vreg31
896B		%vreg34<def,tied1> = LSRWRd %vreg33<tied0>, %SREG<imp-def,dead>; DLDREGS:%vreg34 DREGS:%vreg33
912B		%vreg35<def,tied1> = ANDIWRdK %vreg34<tied0>, 13107, %SREG<imp-def,dead>; DLDREGS:%vreg35,%vreg34
928B		%vreg36<def,tied1> = ADDWRdRr %vreg32<tied0>, %vreg35<kill>, %SREG<imp-def,dead>; DREGS:%vreg36 DLDREGS:%vreg32,%vreg35
944B		%vreg37<def,tied1> = LSRWRd %vreg36<tied0>, %SREG<imp-def,dead>; DREGS:%vreg37,%vreg36
960B		%vreg38<def,tied1> = LSRWRd %vreg37<tied0>, %SREG<imp-def,dead>; DREGS:%vreg38,%vreg37
976B		%vreg39<def,tied1> = LSRWRd %vreg38<tied0>, %SREG<imp-def,dead>; DREGS:%vreg39,%vreg38
992B		%vreg40<def,tied1> = LSRWRd %vreg39<tied0>, %SREG<imp-def,dead>; DREGS:%vreg40,%vreg39
1008B		%vreg41<def,tied1> = ADDWRdRr %vreg36<tied0>, %vreg40<kill>, %SREG<imp-def,dead>; DLDREGS:%vreg41 DREGS:%vreg36,%vreg40
1024B		%vreg42<def,tied1> = ANDIWRdK %vreg41<tied0>, 3855, %SREG<imp-def,dead>; DLDREGS:%vreg42,%vreg41
1040B		%vreg43<def> = COPY %vreg42:sub_lo; GPR8:%vreg43 DLDREGS:%vreg42
1056B		%vreg44<def> = LDIRdK 1; LD8:%vreg44
1072B		MULRdRr %vreg43, %vreg44, %R1<imp-def>, %R0<imp-def>, %SREG<imp-def,dead>; GPR8:%vreg43 LD8:%vreg44
1088B		%vreg45<def> = COPY %R0; GPR8:%vreg45
1104B		%vreg46<def> = COPY %R1; GPR8:%vreg46
1120B		%R1<def,tied1> = EORRdRr %R1<tied0>, %R1, %SREG<imp-def>
1136B		%R1<def,tied1> = EORRdRr %R1<tied0>, %R1, %SREG<imp-def>
1152B		%vreg47<def,tied1> = ADDRdRr %vreg46<tied0>, %vreg43, %SREG<imp-def,dead>; GPR8:%vreg47,%vreg46,%vreg43
1168B		%vreg48<def> = COPY %vreg42:sub_hi; GPR8:%vreg48 DLDREGS:%vreg42
1184B		%vreg49<def,tied1> = ADDRdRr %vreg47<tied0>, %vreg48<kill>, %SREG<imp-def,dead>; GPR8:%vreg49,%vreg47,%vreg48
1200B		%vreg51<def> = IMPLICIT_DEF; DREGS:%vreg51
1216B		%vreg50<def,tied1> = INSERT_SUBREG %vreg51<tied0>, %vreg49<kill>, sub_lo; DREGS:%vreg50,%vreg51 GPR8:%vreg49
1232B		%vreg52<def,tied1> = LSLWRd %vreg50<tied0>, %SREG<imp-def,dead>; DREGS:%vreg52,%vreg50
1248B		%vreg53<def,tied1> = LSLWRd %vreg52<tied0>, %SREG<imp-def,dead>; DREGS:%vreg53,%vreg52
1264B		%vreg54<def,tied1> = LSLWRd %vreg53<tied0>, %SREG<imp-def,dead>; DREGS:%vreg54,%vreg53
1280B		%vreg55<def,tied1> = LSLWRd %vreg54<tied0>, %SREG<imp-def,dead>; DREGS:%vreg55,%vreg54
1296B		%vreg56<def,tied1> = LSLWRd %vreg55<tied0>, %SREG<imp-def,dead>; DREGS:%vreg56,%vreg55
1312B		%vreg57<def,tied1> = LSLWRd %vreg56<tied0>, %SREG<imp-def,dead>; DREGS:%vreg57,%vreg56
1328B		%vreg58<def,tied1> = LSLWRd %vreg57<tied0>, %SREG<imp-def,dead>; DREGS:%vreg58,%vreg57
1344B		%vreg59<def,tied1> = LSLWRd %vreg58<tied0>, %SREG<imp-def,dead>; DREGS:%vreg59,%vreg58
1360B		%vreg60<def> = ZEXT %vreg45, %SREG<imp-def,dead>; DREGS:%vreg60 GPR8:%vreg45
1376B		%vreg61<def,tied1> = ORWRdRr %vreg60<tied0>, %vreg59<kill>, %SREG<imp-def,dead>; DREGS:%vreg61,%vreg60,%vreg59
1392B		%vreg62<def,tied1> = LSRWRd %vreg61<tied0>, %SREG<imp-def,dead>; DREGS:%vreg62,%vreg61
1408B		%vreg63<def,tied1> = LSRWRd %vreg62<tied0>, %SREG<imp-def,dead>; DREGS:%vreg63,%vreg62
1424B		%vreg64<def,tied1> = LSRWRd %vreg63<tied0>, %SREG<imp-def,dead>; DREGS:%vreg64,%vreg63
1440B		%vreg65<def,tied1> = LSRWRd %vreg64<tied0>, %SREG<imp-def,dead>; DREGS:%vreg65,%vreg64
1456B		%vreg66<def,tied1> = LSRWRd %vreg65<tied0>, %SREG<imp-def,dead>; DREGS:%vreg66,%vreg65
1472B		%vreg67<def,tied1> = LSRWRd %vreg66<tied0>, %SREG<imp-def,dead>; DREGS:%vreg67,%vreg66
1488B		%vreg68<def,tied1> = LSRWRd %vreg67<tied0>, %SREG<imp-def,dead>; DREGS:%vreg68,%vreg67
1504B		%vreg69<def,tied1> = LSRWRd %vreg68<tied0>, %SREG<imp-def,dead>; DREGS:%vreg69,%vreg68
1520B		%vreg70<def,tied1> = LSRWRd %vreg1<tied0>, %SREG<imp-def,dead>; DREGS:%vreg70,%vreg1
1536B		%vreg71<def,tied1> = ORWRdRr %vreg1<tied0>, %vreg70<kill>, %SREG<imp-def,dead>; DREGS:%vreg71,%vreg1,%vreg70
1552B		%vreg72<def,tied1> = LSRWRd %vreg71<tied0>, %SREG<imp-def,dead>; DREGS:%vreg72,%vreg71
1568B		%vreg73<def,tied1> = LSRWRd %vreg72<tied0>, %SREG<imp-def,dead>; DREGS:%vreg73,%vreg72
1584B		%vreg74<def,tied1> = ORWRdRr %vreg71<tied0>, %vreg73<kill>, %SREG<imp-def,dead>; DREGS:%vreg74,%vreg71,%vreg73
1600B		%vreg75<def,tied1> = LSRWRd %vreg74<tied0>, %SREG<imp-def,dead>; DREGS:%vreg75,%vreg74
1616B		%vreg76<def,tied1> = LSRWRd %vreg75<tied0>, %SREG<imp-def,dead>; DREGS:%vreg76,%vreg75
1632B		%vreg77<def,tied1> = LSRWRd %vreg76<tied0>, %SREG<imp-def,dead>; DREGS:%vreg77,%vreg76
1648B		%vreg78<def,tied1> = LSRWRd %vreg77<tied0>, %SREG<imp-def,dead>; DREGS:%vreg78,%vreg77
1664B		%vreg79<def,tied1> = ORWRdRr %vreg74<tied0>, %vreg78<kill>, %SREG<imp-def,dead>; DREGS:%vreg79,%vreg74,%vreg78
1680B		%vreg80<def,tied1> = LSRWRd %vreg79<tied0>, %SREG<imp-def,dead>; DREGS:%vreg80,%vreg79
1696B		%vreg81<def,tied1> = LSRWRd %vreg80<tied0>, %SREG<imp-def,dead>; DREGS:%vreg81,%vreg80
1712B		%vreg82<def,tied1> = LSRWRd %vreg81<tied0>, %SREG<imp-def,dead>; DREGS:%vreg82,%vreg81
1728B		%vreg83<def,tied1> = LSRWRd %vreg82<tied0>, %SREG<imp-def,dead>; DREGS:%vreg83,%vreg82
1744B		%vreg84<def,tied1> = LSRWRd %vreg83<tied0>, %SREG<imp-def,dead>; DREGS:%vreg84,%vreg83
1760B		%vreg85<def,tied1> = LSRWRd %vreg84<tied0>, %SREG<imp-def,dead>; DREGS:%vreg85,%vreg84
1776B		%vreg86<def,tied1> = LSRWRd %vreg85<tied0>, %SREG<imp-def,dead>; DREGS:%vreg86,%vreg85
1792B		%vreg87<def,tied1> = LSRWRd %vreg86<tied0>, %SREG<imp-def,dead>; DREGS:%vreg87,%vreg86
1808B		%vreg88<def,tied1> = ORWRdRr %vreg79<tied0>, %vreg87<kill>, %SREG<imp-def,dead>; DREGS:%vreg88,%vreg79,%vreg87
1824B		%vreg89<def,tied1> = COMWRd %vreg88<tied0>, %SREG<imp-def,dead>; DREGS:%vreg89,%vreg88
1840B		%vreg90<def,tied1> = LSRWRd %vreg89<tied0>, %SREG<imp-def,dead>; DLDREGS:%vreg90 DREGS:%vreg89
1856B		%vreg91<def,tied1> = ANDIWRdK %vreg90<tied0>, 21845, %SREG<imp-def,dead>; DLDREGS:%vreg91,%vreg90
1872B		%vreg92<def,tied1> = SUBWRdRr %vreg89<tied0>, %vreg91<kill>, %SREG<imp-def,dead>; DLDREGS:%vreg92,%vreg91 DREGS:%vreg89
1888B		%vreg93<def,tied1> = ANDIWRdK %vreg92<tied0>, 13107, %SREG<imp-def,dead>; DLDREGS:%vreg93,%vreg92
1904B		%vreg94<def,tied1> = LSRWRd %vreg92<tied0>, %SREG<imp-def,dead>; DREGS:%vreg94 DLDREGS:%vreg92
1920B		%vreg95<def,tied1> = LSRWRd %vreg94<tied0>, %SREG<imp-def,dead>; DLDREGS:%vreg95 DREGS:%vreg94
1936B		%vreg96<def,tied1> = ANDIWRdK %vreg95<tied0>, 13107, %SREG<imp-def,dead>; DLDREGS:%vreg96,%vreg95
1952B		%vreg97<def,tied1> = ADDWRdRr %vreg93<tied0>, %vreg96<kill>, %SREG<imp-def,dead>; DREGS:%vreg97 DLDREGS:%vreg93,%vreg96
1968B		%vreg98<def,tied1> = LSRWRd %vreg97<tied0>, %SREG<imp-def,dead>; DREGS:%vreg98,%vreg97
1984B		%vreg99<def,tied1> = LSRWRd %vreg98<tied0>, %SREG<imp-def,dead>; DREGS:%vreg99,%vreg98
2000B		%vreg100<def,tied1> = LSRWRd %vreg99<tied0>, %SREG<imp-def,dead>; DREGS:%vreg100,%vreg99
2016B		%vreg101<def,tied1> = LSRWRd %vreg100<tied0>, %SREG<imp-def,dead>; DREGS:%vreg101,%vreg100
2032B		%vreg102<def,tied1> = ADDWRdRr %vreg97<tied0>, %vreg101<kill>, %SREG<imp-def,dead>; DLDREGS:%vreg102 DREGS:%vreg97,%vreg101
2048B		%vreg103<def,tied1> = ANDIWRdK %vreg102<tied0>, 3855, %SREG<imp-def,dead>; DLDREGS:%vreg103,%vreg102
2064B		%vreg104<def> = COPY %vreg103:sub_lo; GPR8:%vreg104 DLDREGS:%vreg103
2080B		MULRdRr %vreg104, %vreg44, %R1<imp-def>, %R0<imp-def>, %SREG<imp-def,dead>; GPR8:%vreg104 LD8:%vreg44
2096B		%vreg105<def> = COPY %R0; GPR8:%vreg105
2112B		%vreg106<def> = COPY %R1; GPR8:%vreg106
2128B		%R1<def,tied1> = EORRdRr %R1<tied0>, %R1, %SREG<imp-def>
2144B		%R1<def,tied1> = EORRdRr %R1<tied0>, %R1, %SREG<imp-def>
2160B		%vreg107<def,tied1> = ADDRdRr %vreg106<tied0>, %vreg104, %SREG<imp-def,dead>; GPR8:%vreg107,%vreg106,%vreg104
2176B		%vreg108<def> = COPY %vreg103:sub_hi; GPR8:%vreg108 DLDREGS:%vreg103
2192B		%vreg109<def,tied1> = ADDRdRr %vreg107<tied0>, %vreg108<kill>, %SREG<imp-def,dead>; GPR8:%vreg109,%vreg107,%vreg108
2208B		%vreg111<def> = IMPLICIT_DEF; DREGS:%vreg111
2224B		%vreg110<def,tied1> = INSERT_SUBREG %vreg111<tied0>, %vreg109<kill>, sub_lo; DREGS:%vreg110,%vreg111 GPR8:%vreg109
2240B		%vreg112<def,tied1> = LSLWRd %vreg110<tied0>, %SREG<imp-def,dead>; DREGS:%vreg112,%vreg110
2256B		%vreg113<def,tied1> = LSLWRd %vreg112<tied0>, %SREG<imp-def,dead>; DREGS:%vreg113,%vreg112
2272B		%vreg114<def,tied1> = LSLWRd %vreg113<tied0>, %SREG<imp-def,dead>; DREGS:%vreg114,%vreg113
2288B		%vreg115<def,tied1> = LSLWRd %vreg114<tied0>, %SREG<imp-def,dead>; DREGS:%vreg115,%vreg114
2304B		%vreg116<def,tied1> = LSLWRd %vreg115<tied0>, %SREG<imp-def,dead>; DREGS:%vreg116,%vreg115
2320B		%vreg117<def,tied1> = LSLWRd %vreg116<tied0>, %SREG<imp-def,dead>; DREGS:%vreg117,%vreg116
2336B		%vreg118<def,tied1> = LSLWRd %vreg117<tied0>, %SREG<imp-def,dead>; DREGS:%vreg118,%vreg117
2352B		%vreg119<def,tied1> = LSLWRd %vreg118<tied0>, %SREG<imp-def,dead>; DREGS:%vreg119,%vreg118
2368B		%vreg120<def> = ZEXT %vreg105, %SREG<imp-def,dead>; DREGS:%vreg120 GPR8:%vreg105
2384B		%vreg121<def,tied1> = ORWRdRr %vreg120<tied0>, %vreg119<kill>, %SREG<imp-def,dead>; DREGS:%vreg121,%vreg120,%vreg119
2400B		%vreg122<def,tied1> = LSRWRd %vreg121<tied0>, %SREG<imp-def,dead>; DREGS:%vreg122,%vreg121
2416B		%vreg123<def,tied1> = LSRWRd %vreg122<tied0>, %SREG<imp-def,dead>; DREGS:%vreg123,%vreg122
2432B		%vreg124<def,tied1> = LSRWRd %vreg123<tied0>, %SREG<imp-def,dead>; DREGS:%vreg124,%vreg123
2448B		%vreg125<def,tied1> = LSRWRd %vreg124<tied0>, %SREG<imp-def,dead>; DREGS:%vreg125,%vreg124
2464B		%vreg126<def,tied1> = LSRWRd %vreg125<tied0>, %SREG<imp-def,dead>; DREGS:%vreg126,%vreg125
2480B		%vreg127<def,tied1> = LSRWRd %vreg126<tied0>, %SREG<imp-def,dead>; DREGS:%vreg127,%vreg126
2496B		%vreg128<def,tied1> = LSRWRd %vreg127<tied0>, %SREG<imp-def,dead>; DREGS:%vreg128,%vreg127
2512B		%vreg129<def,tied1> = LSRWRd %vreg128<tied0>, %SREG<imp-def,dead>; IWREGS:%vreg129 DREGS:%vreg128
2528B		%vreg130<def,tied1> = ADIWRdK %vreg129<tied0>, 16, %SREG<imp-def,dead>; IWREGS:%vreg130,%vreg129
2544B		CPWRdRr %vreg2, %vreg6, %SREG<imp-def>; DREGS:%vreg2 DLDREGS:%vreg6
2560B		RBRNEk <BB#1>, %SREG<imp-use>
2576B		RJMPk <BB#2>
	    Successors according to CFG: BB#2(?%) BB#1(?%)

# End machine code for function pow.

gergoerdi · 2017-05-10T06:34:56Z

********** PROCESS IMPLICIT DEFS **********
********** Function: pow
BB#0 has 2 implicit defs.
Processing %vreg111<def> = IMPLICIT_DEF; DREGS:%vreg111
Processing %vreg51<def> = IMPLICIT_DEF; DREGS:%vreg51

gergoerdi · 2017-05-10T06:57:14Z

That's because

  MachineFunction::iterator I;
  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
  MF->insert(I, trueMBB);
  MF->insert(I, falseMBB);

is off by one compared to the original code. So it should be

  MachineFunction::iterator I;
  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
  if (I != MF->end()) ++I;
  MF->insert(I, trueMBB);
  MF->insert(I, falseMBB);

… same spot as the original MBB (avr-rust/rust-legacy-fork#49)

gergoerdi · 2017-05-11T11:21:06Z

How do I add some kind of 'has-patch' tag?

shepmaster · 2017-05-11T15:31:33Z

How do I add some kind of 'has-patch' tag?

Once you've got a commit that's been merged into LLVM, notify us here and we can cherry-pick it into our LLVM fork.

I'm not 100% sure what the LLVM submission process is, but I'm sure @dylanmckay would be willing to point the way if you can't find anything online.

dylanmckay · 2017-05-11T22:26:28Z

I'm not 100% sure what the LLVM submission process is, but I'm sure @dylanmckay would be willing to point the way if you can't find anything online.

This guide is really good. Prefer submitting the patch via Phabricator instead of email because it's much easier to review.

Feel free to add me as a reviewer (my phab username is dylanmckay) and I can sign off and commit it for you.

Nice debugging!

… same spot as the original MBB (avr-rust/rust-legacy-fork#49)

dylanmckay · 2017-05-13T00:37:21Z

I've added the testcase from this issue into the LLVM patch and I've also upstreamed it in r302973.

… same spot Contributed by Dr. Gergő Érdi. Fixes a bug. Raised from (avr-rust/rust-legacy-fork#49). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302973 91177308-0d34-0410-b5e6-96231b3b80d8

… same spot Contributed by Dr. Gergő Érdi. Fixes a bug. Raised from (avr-rust/rust-legacy-fork#49). llvm-svn=302973

dylanmckay · 2017-05-13T00:41:21Z

Cherry picked into avr-rust in 6df5771.

Thanks for the work @gergoerdi!

jackpot51 · 2017-05-13T00:46:14Z

@gergoerdi Were you able to compile libcore with these changes?

… same spot Contributed by Dr. Gergő Érdi. Fixes a bug. Raised from (avr-rust/rust-legacy-fork#49). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302973 91177308-0d34-0410-b5e6-96231b3b80d8

shepmaster · 2017-05-13T04:29:54Z

@jackpot51 you can see @gergoerdi's blog post and comments on Reddit.

TL;DR, no. Like we've needed to do before, a subset of libcore was created.

gergoerdi · 2017-05-13T09:36:33Z

@shepmaster @dylanmckay Thanks for covering the last mile on this. I'd like to add similar test cases to my other commits, so I tried following http://llvm.org/docs/TestingGuide.html. How do I run LLVM tests from inside the rustc build tree? I've tried

$ pwd # As you can see, this is inside rustc's build tree
/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/llvm/build
$ ./bin/llvm-lit ../../../../../rust/src/llvm/test/CodeGen/AVR/
llvm-lit: /home/cactus/prog/rust/rust-avr/rust/src/llvm/test/lit.cfg:159: fatal: No site specific configuration available!

dylanmckay · 2017-05-13T09:40:25Z

That looks to be related to the fact that LLVM is compiled inside the Rust build dir.

Normally when you compile and run LLVM, it will run a configure script which will fill a file named lit.site.cfg with configure settings.

I'm not sure how to work around it, but I know for certain that if you build LLVM on its own, it will work fine.

I think in order to compile it on its own, all you need to do it cmake ~/path/to/rust/src/llvm -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR -DCMAKE_BUILD_TYPE=Debug && make

dylanmckay · 2017-05-31T06:13:45Z

The fix has been upstreamed in r302973.

dylanmckay · 2017-05-31T06:44:10Z

Fix has been cherry picked into avr-support branch in 301cc4e.

… same spot Contributed by Dr. Gergő Érdi. Fixes a bug. Raised from (avr-rust/rust-legacy-fork#49). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302973 91177308-0d34-0410-b5e6-96231b3b80d8

gergoerdi added a commit to gergoerdi/llvm-avr that referenced this issue May 10, 2017

[AVR] When lowering Select8/Select16, put newly generated MBBs in the…

c7d5217

… same spot as the original MBB (avr-rust/rust-legacy-fork#49)

gergoerdi mentioned this issue May 10, 2017

Switch lookup gets turned into a branch to a wrong address #46

Closed

shepmaster added the A-llvm Affects the LLVM AVR backend label May 10, 2017

gergoerdi mentioned this issue May 11, 2017

IL ordering bug? #51

Closed

shepmaster added the has-reduced-testcase A small LLVM IR file exists that demonstrates the problem label May 11, 2017

gergoerdi added a commit to gergoerdi/llvm-avr that referenced this issue May 12, 2017

[AVR] When lowering Select8/Select16, put newly generated MBBs in the…

2838d98

… same spot as the original MBB (avr-rust/rust-legacy-fork#49)

dylanmckay closed this as completed May 13, 2017

dylanmckay added the has-llvm-commit This issue should be fixed in upstream LLVM label May 13, 2017

gergoerdi mentioned this issue May 13, 2017

Experimental AVR target improvements avr-rust/llvm#1

Merged

gergoerdi mentioned this issue May 20, 2017

Another MBB reordering bug #62

Closed

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Final continuation jump missing from MBB #49

Final continuation jump missing from MBB #49

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Final continuation jump missing from MBB #49

Final continuation jump missing from MBB #49

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