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SIMD: load/store lane, any_true, q-format multiply, i64x2.widen #196

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Merged
merged 13 commits into from
Jan 19, 2021
Merged

SIMD: load/store lane, any_true, q-format multiply, i64x2.widen #196

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b789024
Add i64x2.widen_high/low_i32x4_s/u instructions
Jan 11, 2021
d111af1
Add v128.loadNlane and v128.storeNlane instructions
Jan 11, 2021
9dca550
Add i16x8.q15mulr_sat_s instruction
Jan 11, 2021
530b090
Add i64x2.bitmask instruction
Jan 11, 2021
0b8246d
Remove i16x8.any_true and i32x4.any_true, rename i8x16.any_true as v1…
Jan 11, 2021
4660652
Skip tests.
Jan 18, 2021
0b52e1e
Merge branch 'main' into simd-new-instructions
Jan 18, 2021
8055318
Disable tests that use an explicit memory index
Jan 19, 2021
9517b20
Test cases for new instructions
Jan 19, 2021
a17dc28
Parser bug fixes
Jan 19, 2021
f232890
Run cargo fmt
Jan 19, 2021
e060e46
Require the memory keyword for the memory index, if present
Jan 19, 2021
ecbd378
Uncomment disabled tests, but make them use the memory keyword for th…
Jan 19, 2021
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42 changes: 39 additions & 3 deletions crates/wasmparser/src/binary_reader.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1645,9 +1645,41 @@ impl<'a> BinaryReader<'a> {
0x50 => Operator::V128Or,
0x51 => Operator::V128Xor,
0x52 => Operator::V128Bitselect,
0x58 => Operator::V128Load8Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(16)?,
},
0x59 => Operator::V128Load16Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(8)?,
},
0x5a => Operator::V128Load32Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(4)?,
},
0x5b => Operator::V128Load64Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(2)?,
},
0x5c => Operator::V128Store8Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(16)?,
},
0x5d => Operator::V128Store16Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(8)?,
},
0x5e => Operator::V128Store32Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(4)?,
},
0x5f => Operator::V128Store64Lane {
memarg: self.read_memarg()?,
lane: self.read_lane_index(2)?,
},
0x60 => Operator::I8x16Abs,
0x61 => Operator::I8x16Neg,
0x62 => Operator::I8x16AnyTrue,
0x62 => Operator::V128AnyTrue,
0x63 => Operator::I8x16AllTrue,
0x64 => Operator::I8x16Bitmask,
0x65 => Operator::I8x16NarrowI16x8S,
Expand All @@ -1668,7 +1700,6 @@ impl<'a> BinaryReader<'a> {
0x7b => Operator::I8x16RoundingAverageU,
0x80 => Operator::I16x8Abs,
0x81 => Operator::I16x8Neg,
0x82 => Operator::I16x8AnyTrue,
0x83 => Operator::I16x8AllTrue,
0x84 => Operator::I16x8Bitmask,
0x85 => Operator::I16x8NarrowI32x4S,
Expand All @@ -1693,12 +1724,12 @@ impl<'a> BinaryReader<'a> {
0x99 => Operator::I16x8MaxU,
0x9a => Operator::I16x8ExtMulLowI8x16S,
0x9b => Operator::I16x8RoundingAverageU,
0x9c => Operator::I16x8Q15MulrSatS,
0x9d => Operator::I16x8ExtMulHighI8x16S,
0x9e => Operator::I16x8ExtMulLowI8x16U,
0x9f => Operator::I16x8ExtMulHighI8x16U,
0xa0 => Operator::I32x4Abs,
0xa1 => Operator::I32x4Neg,
0xa2 => Operator::I32x4AnyTrue,
0xa3 => Operator::I32x4AllTrue,
0xa4 => Operator::I32x4Bitmask,
0xa7 => Operator::I32x4WidenLowI16x8S,
Expand All @@ -1721,6 +1752,11 @@ impl<'a> BinaryReader<'a> {
0xbe => Operator::I32x4ExtMulLowI16x8U,
0xbf => Operator::I32x4ExtMulHighI16x8U,
0xc1 => Operator::I64x2Neg,
0xc4 => Operator::I64x2Bitmask,
0xc7 => Operator::I64x2WidenLowI32x4S,
0xc8 => Operator::I64x2WidenHighI32x4S,
0xc9 => Operator::I64x2WidenLowI32x4U,
0xca => Operator::I64x2WidenHighI32x4U,
0xcb => Operator::I64x2Shl,
0xcc => Operator::I64x2ShrS,
0xcd => Operator::I64x2ShrU,
Expand Down
77 changes: 70 additions & 7 deletions crates/wasmparser/src/operators_validator.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1604,7 +1604,8 @@ impl OperatorValidator {
| Operator::I64x2ExtMulLowI32x4S
| Operator::I64x2ExtMulHighI32x4S
| Operator::I64x2ExtMulLowI32x4U
| Operator::I64x2ExtMulHighI32x4U => {
| Operator::I64x2ExtMulHighI32x4U
| Operator::I16x8Q15MulrSatS => {
self.check_simd_enabled()?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(Type::V128))?;
Expand Down Expand Up @@ -1648,7 +1649,11 @@ impl OperatorValidator {
| Operator::I32x4WidenLowI16x8S
| Operator::I32x4WidenHighI16x8S
| Operator::I32x4WidenLowI16x8U
| Operator::I32x4WidenHighI16x8U => {
| Operator::I32x4WidenHighI16x8U
| Operator::I64x2WidenLowI32x4S
| Operator::I64x2WidenHighI32x4S
| Operator::I64x2WidenLowI32x4U
| Operator::I64x2WidenHighI32x4U => {
self.check_simd_enabled()?;
self.pop_operand(Some(Type::V128))?;
self.push_operand(Type::V128)?;
Expand All @@ -1660,15 +1665,14 @@ impl OperatorValidator {
self.pop_operand(Some(Type::V128))?;
self.push_operand(Type::V128)?;
}
Operator::I8x16AnyTrue
Operator::V128AnyTrue
| Operator::I8x16AllTrue
| Operator::I8x16Bitmask
| Operator::I16x8AnyTrue
| Operator::I16x8AllTrue
| Operator::I16x8Bitmask
| Operator::I32x4AnyTrue
| Operator::I32x4AllTrue
| Operator::I32x4Bitmask => {
| Operator::I32x4Bitmask
| Operator::I64x2Bitmask => {
self.check_simd_enabled()?;
self.pop_operand(Some(Type::V128))?;
self.push_operand(Type::I32)?;
Expand Down Expand Up @@ -1736,7 +1740,66 @@ impl OperatorValidator {
self.pop_operand(Some(idx))?;
self.push_operand(Type::V128)?;
}

Operator::V128Load8Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 0, resources)?;
self.check_simd_lane_index(lane, 16)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
self.push_operand(Type::V128)?;
}
Operator::V128Load16Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 1, resources)?;
self.check_simd_lane_index(lane, 8)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
self.push_operand(Type::V128)?;
}
Operator::V128Load32Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 2, resources)?;
self.check_simd_lane_index(lane, 4)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
self.push_operand(Type::V128)?;
}
Operator::V128Load64Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 3, resources)?;
self.check_simd_lane_index(lane, 2)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
self.push_operand(Type::V128)?;
}
Operator::V128Store8Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 0, resources)?;
self.check_simd_lane_index(lane, 16)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
}
Operator::V128Store16Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 1, resources)?;
self.check_simd_lane_index(lane, 8)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
}
Operator::V128Store32Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 2, resources)?;
self.check_simd_lane_index(lane, 4)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
}
Operator::V128Store64Lane { memarg, lane } => {
self.check_simd_enabled()?;
let idx = self.check_memarg(memarg, 3, resources)?;
self.check_simd_lane_index(lane, 2)?;
self.pop_operand(Some(Type::V128))?;
self.pop_operand(Some(idx))?;
}
Operator::MemoryInit { mem, segment } => {
self.check_bulk_memory_enabled()?;
let ty = self.check_memory_index(mem, resources)?;
Expand Down
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