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Verilog: `elsif #1110

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Merged
merged 1 commit into from
May 21, 2025
Merged

Verilog: `elsif #1110

merged 1 commit into from
May 21, 2025

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kroening
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This adds the `elsif preprocessor directive to the Verilog preprocessor.

@kroening
Verilog: `elsif
cb7d934 
This adds the `elsif preprocessor directive to the Verilog preprocessor.
@kroening kroening marked this pull request as ready for review May 18, 2025 12:28
@tautschnig tautschnig merged commit 6732c86 into main May 21, 2025
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@tautschnig tautschnig deleted the verilog-elsif branch May 21, 2025 03:04
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@tautschnig tautschnig tautschnig approved these changes

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@kroening @tautschnig