Verilog: directives inside `include argument
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kroening
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include argument
This changes the behavior when processing a Verilog preprocessor `include directive. 1. When the argument contains a directive, a better error message is issued. Other tools process (at least some) directives within the argument. 2. When the argument is a file name enclosed in " quotes, the character sequence is used as is, and no string literal processing is performed. This behavior matches what other tools implement. Note that 1800-2017 does not specify the required behavior for either one of these scenarios.
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tautschnig
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Dec 9, 2024
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This changes the behavior when processing a Verilog preprocessor `include directive.
When the argument contains a directive, a better error message is issued. Other tools process (at least some) directives within the argument.
When the argument is a file name enclosed in " quotes, the character sequence is used as is, and no string literal processing is performed. This behavior matches what other tools implement.
Note that 1800-2017 does not specify the required behavior for either one of these scenarios.