Assertion failed '(targetReg == op1Reg) || (targetReg != op3Reg)' during 'Generate code'

[kunalspathak]

// Found by Antigen
// Reduced from 206.63 KB to 1.9 KB.


using System;
using System.Collections.Generic;
using System.Runtime.CompilerServices;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.Arm;
using System.Runtime.Intrinsics.X86;
using System.Numerics;
public class TestClass
{
    public struct S1
    {
        public int int_1;
    }
    static byte s_byte_4 = 1;
    static Vector64<short> s_v64_short_20 = Vector64.Create(94, -2, 3, 3);
    static Vector128<byte> s_v128_byte_28 = Vector128.Create((byte)2);
    static Vector128<ushort> s_v128_ushort_31 = Vector128.Create((ushort)32766);
    Vector64<short> v64_short_70 = Vector64<short>.AllBitsSet;
    Vector128<byte> v128_byte_78 = Vector128.CreateScalar((byte)0);
    Vector128<short> v128_short_80 = Vector128.Create(-2, 0, 2, 94, 3, 0, 3, 0);
    Vector128<ushort> v128_ushort_81 = Vector128<ushort>.AllBitsSet;
    private static List<string> toPrint = new List<string>();
    public void Method0()
    {
        unchecked
        {
            S1 s1_172 = new S1();
            s_v128_ushort_31 = Vector128.LessThan(s_v128_ushort_31 -= Vector128<ushort>.Zero | v128_ushort_81, AdvSimd.AddWideningUpper(v128_ushort_81 & v128_ushort_81, s_v128_byte_28 = v128_byte_78));
            v128_short_80 = AdvSimd.ExtractVector128(AdvSimd.MultiplyByScalar(v128_short_80 - v128_short_80, AdvSimd.MultiplySubtractByScalar(v64_short_70, s_v64_short_20, v64_short_70)), v128_short_80 - v128_short_80, s_byte_4);
            s_v64_short_20 = AdvSimd.ShiftRightLogicalRoundedAdd(v64_short_70 -= v64_short_70 += v64_short_70, v64_short_70 + Vector64<short>.AllBitsSet + v64_short_70 + Vector64<short>.AllBitsSet & v64_short_70, s_byte_4 >>= s1_172.int_1 <<= 15 + 4);
            return;
        }
    }
    public static int Main(string[] args)
    {
        return Antigen();
    }
    public static int Antigen()
    {
        new TestClass().Method0();
        return string.Join(Environment.NewLine, toPrint).GetHashCode();
    }
}
/*
Environment:

set DOTNET_AltJit=Method0
set DOTNET_AltJitName=clrjit_universal_arm64_x64.dll
set DOTNET_EnableWriteXorExecute=0
set DOTNET_JitDisasm=Method0
set DOTNET_JitStressRegs=2
set DOTNET_TieredCompilation=0

Debug: 1639727076

Release: 0
JIT assert failed:
Assertion failed '(targetReg == op1Reg) || (targetReg != op3Reg)' in 'TestClass:Method0():this' during 'Generate code' (IL size 298; hash 0x46e9aa75; FullOpts)

    File: /Users/runner/work/1/s/src/coreclr/jit/hwintrinsiccodegenarm64.cpp Line: 416


*/

This is similar to #114322, but at different location (and for different intrinsics, so opening it a separate issue)

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[JulieLeeMSFT]

Assigned to you, @kunalspathak.

[kunalspathak]

MultiplySubtractByScalar is RMW intrinsic that takes 3 operands. 1st operand is the RMW that also acts as destination.
We have a scenario of MultiplySubtractByScalar(op1, op2, op1) and we mark 2nd operand as delay-free, but cannot mark the 3rd operand as delay-free because it is the same interval as the that of 1st operand i.e. op1. Further, we try to prefer to assign the target register same as that we will assign for 1st operand (because of RMW semantics), however, we see that the 1st operand op1 is not a last use and so we do not want to overwrite it. As a result, we end up in situation that is something like:

targetReg = v7
op1Reg = v16
op2Reg= v8
op3Reg= v7

The RMW semantics rule says that if targetReg != op1Reg, we should do mov targetReg, op1Reg, but if we do that, we will be overwriting the value of 3rd operand that resides in op3Reg.