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JIT assert if a retyped simd32 is CSE'd and needs to have the upper half saved/restored #35620

@tannergooding

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@tannergooding

As per #35421 (comment), it is possible for the genSIMDIntrinsic to assert for any GT_SIMD or GT_HWINTRINSIC which has been retyped if the target type hasn't been actually encountered (and therefore is missing from the SIMD handle cache).

At least at initial glance, it could likely be resolved by setting lvBaseType based on the tree->gtSimdBaseType from the GT_SIMD or GT_HWINTRINSIC (whether tree is one directly or indirectly via GT_IND, GT_OBJ, or GT_ADDR).

category:correctness
theme:hardware-intrinsics
skill-level:intermediate
cost:medium

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Priority:3Work that is nice to havearea-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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