Arm: Free up upper-half register that was not ready because of its association with busy lower-half register #107714
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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AndyAyersMS
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Sep 13, 2024
yes, thanks for reminding. Wanted to run after CI is green, but forgot. |
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/azp run Fuzzlyn |
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/azp run Antigen |
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Azure Pipelines successfully started running 1 pipeline(s). |
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No Fuzzlyn failures on linux/arm |
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…sociation with busy lower-half register (dotnet#107714) * make sure the upperHalf is moved to ready pool when lowerHalf holding DOUBLE interval is done * remove the logging * added test cases * fix a typo * Add missing Xunit reference * Revert "remove the logging" This reverts commit d8f2f17. * better fix to free up upperHalf if lowerHalf is getting freed up * jit format * Revert "remove the logging" This reverts commit d8f2f17. * Handle upperHalf fix similar to lowerHalf code * formatting * jit format
sirntar
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Sep 30, 2024
…sociation with busy lower-half register (dotnet#107714) * make sure the upperHalf is moved to ready pool when lowerHalf holding DOUBLE interval is done * remove the logging * added test cases * fix a typo * Add missing Xunit reference * Revert "remove the logging" This reverts commit d8f2f17. * better fix to free up upperHalf if lowerHalf is getting freed up * jit format * Revert "remove the logging" This reverts commit d8f2f17. * Handle upperHalf fix similar to lowerHalf code * formatting * jit format
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With #107493, we were not releasing the upper half register from getting resolved, which was held back due to the fact that the lower half was occupied by a
TYP_DOUBLEinterval. However, when we free up the lower half, we should also mark the upper-half target as ready for resolution.Fixes: ##107621