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17 changes: 9 additions & 8 deletions src/coreclr/jit/lowerxarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4076,14 +4076,13 @@ GenTree* Lowering::LowerHWIntrinsicCreate(GenTreeHWIntrinsic* node)

var_types unsignedType = varTypeToUnsigned(simdBaseType);

if (op1->OperIs(GT_CAST) && !op1->gtOverflow())
if (op1->OperIs(GT_CAST) && !op1->gtOverflow() &&
(genTypeSize(op1->CastToType()) == genTypeSize(simdBaseType)))
{
assert(op1->TypeIs(TYP_INT) && (genTypeSize(op1->CastToType()) == genTypeSize(simdBaseType)));
op1->AsCast()->gtCastType = unsignedType;
}
else if (op1->OperIs(GT_IND, GT_LCL_FLD))
else if (op1->OperIs(GT_IND, GT_LCL_FLD) && (genTypeSize(op1) == genTypeSize(simdBaseType)))
{
assert(genTypeSize(op1) == genTypeSize(simdBaseType));
op1->gtType = unsignedType;
}
else if (!op1->OperIs(GT_CAST) || (op1->AsCast()->CastToType() != unsignedType))
Expand Down Expand Up @@ -9663,17 +9662,19 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)

if (varTypeIsIntegral(simdBaseType) && op1->OperIsHWIntrinsic())
{
GenTreeHWIntrinsic* childNode = op1->AsHWIntrinsic();
GenTreeHWIntrinsic* childNode = op1->AsHWIntrinsic();
NamedIntrinsic childIntrinsic = childNode->GetHWIntrinsicId();

if (HWIntrinsicInfo::IsVectorCreateScalarUnsafe(childNode->GetHWIntrinsicId()))
if (HWIntrinsicInfo::IsVectorCreateScalar(childIntrinsic) ||
HWIntrinsicInfo::IsVectorCreateScalarUnsafe(childIntrinsic))
{
// We have a very special case of BroadcastScalarToVector(CreateScalarUnsafe(op1))
// We have a very special case of BroadcastScalarToVector(CreateScalar/Unsafe(op1))
//
// This is one of the only instructions where it supports taking integer types from
// a SIMD register or directly as a scalar from memory. Most other instructions, in
// comparison, take such values from general-purpose registers instead.
//
// Because of this, we're going to remove the CreateScalarUnsafe and try to contain
// Because of this, we're going to remove the CreateScalar/Unsafe and try to contain
// op1 directly, we'll then special case the codegen to materialize the value into a
// SIMD register in the case it is marked optional and doesn't get spilled.

Expand Down
44 changes: 44 additions & 0 deletions src/tests/JIT/Regression/JitBlue/Runtime_113829/Runtime_113829.cs
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

// Generated by Fuzzlyn v2.5 on 2025-03-23 15:10:25
// Run on X64 Windows
// Seed: 14181260275910254012-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86avx512fx64,x86bmi1,x86bmi1x64,x86bmi2,x86bmi2x64,x86fma,x86lzcnt,x86lzcntx64,x86pclmulqdq,x86popcnt,x86popcntx64,x86sse,x86ssex64,x86sse2,x86sse2x64,x86sse3,x86sse41,x86sse41x64,x86sse42,x86sse42x64,x86ssse3,x86x86base
// Reduced from 68.9 KiB to 0.3 KiB in 00:01:38
// Problem() Hits JIT assert in Debug:
// Assertion failed 'genTypeSize(op1) == genTypeSize(simdBaseType)' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Lowering nodeinfo' (IL size 20; hash 0xade6b36b; MinOpts)

// Generated by Fuzzlyn v2.5 on 2025-03-23 15:09:24
// Run on X64 Windows
// Seed: 3022985173499088836-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86avx512fx64,x86bmi1,x86bmi1x64,x86bmi2,x86bmi2x64,x86fma,x86lzcnt,x86lzcntx64,x86pclmulqdq,x86popcnt,x86popcntx64,x86sse,x86ssex64,x86sse2,x86sse2x64,x86sse3,x86sse41,x86sse41x64,x86sse42,x86sse42x64,x86ssse3,x86x86base
// Reduced from 26.2 KiB to 0.3 KiB in 00:01:05
// Problem2() Hits JIT assert in Debug:
// Assertion failed 'op1->TypeIs(TYP_INT) && (genTypeSize(op1->CastToType()) == genTypeSize(simdBaseType))' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Lowering nodeinfo' (IL size 31; hash 0xade6b36b; MinOpts)
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;
using Xunit;

public class C0
{
public sbyte F4;
}

public class Runtime_113829
{
[Fact]
public static void Problem()
{
var vr4 = new C0();
Vector128.CreateScalar((short)vr4.F4);
}

[Fact]
public static void Problem2()
{
if (Sse41.X64.IsSupported)
{
var vr7 = Vector128.CreateScalar(2263564149047927034UL);
Vector256.CreateScalar((short)(sbyte)Sse41.X64.Extract(vr7, 0));
}
}
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<Optimize>False</Optimize>
</PropertyGroup>
<ItemGroup>
<Compile Include="$(MSBuildProjectName).cs" />
</ItemGroup>
</Project>
36 changes: 36 additions & 0 deletions src/tests/JIT/Regression/JitBlue/Runtime_113832/Runtime_113832.cs
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

// Generated by Fuzzlyn v2.5 on 2025-03-23 15:25:27
// Run on X86 Windows
// Seed: 916448399438567841-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86bmi1,x86bmi2,x86fma,x86lzcnt,x86pclmulqdq,x86popcnt,x86sse,x86sse2,x86sse3,x86sse41,x86sse42,x86ssse3,x86x86base
// Reduced from 63.4 KiB to 0.7 KiB in 00:02:21
// Hits JIT assert in Release:
// Assertion failed '(consume == 0) || (ComputeAvailableSrcCount(tree) == consume)' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Linear scan register alloc' (IL size 68; hash 0xade6b36b; FullOpts)
using System;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;
using Xunit;

public class Runtime_113832
{
public static byte s_4;

[Fact]
public static void Problem()
{
if (Avx512F.VL.IsSupported)
{
var vr9 = Vector128.Create<ulong>(0);
var vr10 = (ulong)s_4;
var vr11 = Vector128.CreateScalar(vr10);
var vr12 = Avx2.BroadcastScalarToVector128(vr11);
var vr13 = (byte)0;
var vr14 = Vector256.CreateScalar(vr13);
var vr15 = (ulong)Avx2.MoveMask(vr14);
var vr16 = Vector128.Create<ulong>(vr15);
var vr17 = Avx512F.VL.TernaryLogic(vr9, vr12, vr16, 1);
Console.WriteLine(vr17);
}
}
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<Optimize>True</Optimize>
</PropertyGroup>
<ItemGroup>
<Compile Include="$(MSBuildProjectName).cs" />
</ItemGroup>
</Project>
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