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JIT: Optimize movzx after setcc #66245

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Merged
merged 6 commits into from
Mar 7, 2022
Merged

JIT: Optimize movzx after setcc #66245

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1191d6d
Optimize movzx after setcc
EgorBo Mar 5, 2022
dde2c1e
fix build error
EgorBo Mar 5, 2022
9110760
Let's try this
EgorBo Mar 5, 2022
3977f17
add floats
EgorBo Mar 6, 2022
22f3d20
Use Jakob's approach
EgorBo Mar 7, 2022
cd8f1a9
Update gentree.cpp
EgorBo Mar 7, 2022
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33 changes: 31 additions & 2 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6294,6 +6294,21 @@ void CodeGen::genCompareFloat(GenTree* treeNode)
ins = (op1Type == TYP_FLOAT) ? INS_ucomiss : INS_ucomisd;
cmpAttr = emitTypeSize(op1Type);

var_types targetType = treeNode->TypeGet();

// Clear target reg in advance via "xor reg,reg" to avoid movzx after SETCC
if ((targetReg != REG_NA) && (op1->GetRegNum() != targetReg) && (op2->GetRegNum() != targetReg) &&
!varTypeIsByte(targetType))
{
// memory loads might still use target reg here so we can't clear it
if ((op1->isUsedFromReg() || op1->isContainedFltOrDblImmed()) &&
(op2->isUsedFromReg() || op2->isContainedFltOrDblImmed()))
{
instGen_Set_Reg_To_Zero(emitTypeSize(TYP_I_IMPL), targetReg);
targetType = TYP_BOOL; // just a tip for inst_SETCC that movzx is not needed
}
}

GetEmitter()->emitInsBinary(ins, cmpAttr, op1, op2);

// Are we evaluating this into a register?
Expand All @@ -6309,7 +6324,7 @@ void CodeGen::genCompareFloat(GenTree* treeNode)
condition = GenCondition(GenCondition::P);
}

inst_SETCC(condition, treeNode->TypeGet(), targetReg);
inst_SETCC(condition, targetType, targetReg);
genProduceReg(tree);
}
}
Expand Down Expand Up @@ -6438,6 +6453,8 @@ void CodeGen::genCompareInt(GenTree* treeNode)
// Sign jump optimization should only be set the following check
assert((tree->gtFlags & GTF_RELOP_SJUMP_OPT) == 0);

var_types targetType = tree->TypeGet();

if (canReuseFlags && emit->AreFlagsSetToZeroCmp(op1->GetRegNum(), emitTypeSize(type), tree->OperGet()))
{
JITDUMP("Not emitting compare due to flags being already set\n");
Expand All @@ -6449,13 +6466,25 @@ void CodeGen::genCompareInt(GenTree* treeNode)
}
else
{
// Clear target reg in advance via "xor reg,reg" to avoid movzx after SETCC
if ((targetReg != REG_NA) && (op1->GetRegNum() != targetReg) && (op2->GetRegNum() != targetReg) &&
!varTypeIsByte(targetType))
{
// memory loads might still use target reg here so we can't clear it
if ((op1->isUsedFromReg() || op1->isContainedIntOrIImmed()) &&
(op2->isUsedFromReg() || op2->isContainedIntOrIImmed()))
{
instGen_Set_Reg_To_Zero(emitTypeSize(TYP_I_IMPL), targetReg);
targetType = TYP_BOOL; // just a tip for inst_SETCC that movzx is not needed
}
}
emit->emitInsBinary(ins, emitTypeSize(type), op1, op2);
}

// Are we evaluating this into a register?
if (targetReg != REG_NA)
{
inst_SETCC(GenCondition::FromIntegralRelop(tree), tree->TypeGet(), targetReg);
inst_SETCC(GenCondition::FromIntegralRelop(tree), targetType, targetReg);
genProduceReg(tree);
}
}
Expand Down