Workaround PSRAM cache invalid'n by reading flash #2551
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Fixes #2537 While waiting for a working direct cache flush routine, try and force the cache to evict all PSRAM values by reading a bunch of flash addresses (which share the XIP cache). This hurts performance when PSRAM is not used, but is required for correctness until we have a working XIP flush.
gmx from the RPI forums came up with this hack and it seems to work! https://forums.raspberrypi.com/viewtopic.php?p=2262371#p2262371
earlephilhower
force-pushed
the
psramcacheflush
branch
from
b0b6c46 to
4ce9d14
Compare
earlephilhower
changed the title
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Fixes #2537
While waiting for a working direct cache flush routine, try and force the cache to evict all PSRAM values by reading a bunch of flash addresses (which share the XIP cache). This hurts performance when PSRAM is not used, but is required for correctness until we have a working XIP flush.