Runtime Flash Clock detection #11903
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Updated source frequency handling for ESP32 and ESP32S3 targets.
Replaced FLASH_SPI0_BASE with DR_REG_SPI0_BASE for clock register access.
Refactor flash frequency functions to use ESP-IDF HAL for better maintainability and chip-specific handling.
Removed isFlashHighPerformanceModeEnabled function declaration.
Removed check for High Performance Mode in chip debug report.
Enhanced the documentation for the getFlashClockDivider function and added handling for modern chips using the SPIMEM structure.
Updated includes for modern ESP32 chips to prioritize newer spi_mem_c_struct.h.
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Test Results 76 files 76 suites 13m 40s ⏱️ Results for commit 3d1180d. ♻️ This comment has been updated with latest results. |
Memory usage test (comparing PR against master branch)The table below shows the summary of memory usage change (decrease - increase) in bytes and percentage for each target.
Click to expand the detailed deltas report [usage change in BYTES]
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me-no-dev
approved these changes
Oct 7, 2025
P-R-O-C-H-Y
approved these changes
Oct 8, 2025
P-R-O-C-H-Y
added
Status: Pending Merge
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The PR provides the real flash clock speed and adds the P4/C5 flash chip mode. Fixes the wrong values for C6, H4 and C2
In a follow up PR the magic flash chip routines can be removed and replaced with the real values.
@me-no-dev