RISC-V support #3

ilya-epifanov · 2020-04-01T19:39:46Z

I know it's a lot of code duplication, so I made it in two commits. One which copies the async-cortex-m and another one with the necessary adjustments.

It works just fine on an RV32IMAC VexRiscv softcore

mkroening · 2020-04-01T21:42:41Z

Since the changes are small adjustments regarding architecture specific bits, would it make sense to incorporate these changes via Cargo features? That way any general changes would not have to be doubled and the architecture specific differences would be easier to compare. The crate could then be renamed to async-embedded for example, to not contain links to the architecture in the name.

Then again this is a Proof of Concept and there might be some proper abstractions in the works, so I'm not sure if that would be worth it.

ilya-epifanov · 2020-04-03T11:14:59Z

@mwkroening I ended up using features anyway, to select a suitable WFI/E/SEV implementation, since RISC-V doesn't define a standard way to do SEV

ilya-epifanov · 2020-04-03T11:38:59Z

async-riscv/src/lib.rs

+    }
+}
+
+#[cfg(feature = "wait-nop")]


@mwkroening @japaric I can move ARM implementations here, too. The rest of the crate is generic and works both for ARM and for RISC-V.

I like where this goes, but I have no authority here, so someone else would need to review this.

…Added several RISC-V implementations of `WFE/SEV`, as RISC-V leaves implementation of these to SoC designers.

… Cortex-M and RISC-V ISA's

ilya-epifanov · 2020-04-27T21:59:52Z

@mwkroening @Disasm please take a look.
The ARM portion still runs without problems on an nRF52-DK.
The RISC-V part runs smoothly on a VexRiscV with default-features = false, features = ["isa-riscv", "riscv-wait-wfi-single-hart"]

Disasm · 2020-04-28T01:23:44Z

async-embedded/src/lib.rs

+pub mod task;
+pub mod unsync;
+
+#[cfg(feature = "isa-cortex-m")]


I'd rather replace this with architecture autodetection (with built-in cfgs or build.rs)

Unfortunately, we can't do that on stable yet. I need to conditionally depend on cortex-m, ccortex-m-udf and riscv crates. The fix for rust-lang/cargo#2524 has landed in nightly-2020-02-23.

I mean, I can change the #[cfg(...)] stuff but the user would still have to specify features = ["isa-..."] when depending on the crate.

Once rust-lang/cargo#7914 hits stable, we can remove these features

Strange, this solution works for me just fine:

[target.'cfg(target_arch = "arm")'.dependencies] cortex-m = "*" [target.'cfg(target_arch = "riscv32")'.dependencies] riscv = "*"

Yep, it does. Please see the next commit

Neither master nor this branch work on stable, but both work on beta and nightly just fine.

Disasm · 2020-04-28T01:24:47Z

async-embedded/src/task.rs

@@ -43,7 +41,7 @@ pub async fn r#yield() {
                self.yielded = true;
                // wake ourselves
                cx.waker().wake_by_ref();
-                asm::sev();
+                unsafe { crate::signal_event_ready(); }


I believe this is not required anymore after my fix: https://github.com/ferrous-systems/async-on-embedded/pull/2/files#diff-22ab3da1c5b4e44f95ba9b8000eda448R116
However, sev is required when task is woken from an interrupt context.

Well, your fix included the sev call so I kept it

Disasm · 2020-04-28T17:34:08Z

async-embedded/Cargo.toml

+cortex-m = "0.6.2"
+cortex-m-udf = { path = "../cortex-m-udf" }
+
+[target.'cfg(target_arch = "riscv32")'.dependencies]


Suggested change

[target.'cfg(target_arch = "riscv32")'.dependencies]

[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]

Maybe it's a good idea to add riscv64 too :)

Done. No way for me to test it though

async-embedded/Cargo.toml

Co-Authored-By: Vadim Kaushan <[email protected]>

ilya-epifanov · 2020-04-30T18:33:10Z

@Disasm could you please sign this one off? At least the RISC-V part.

Disasm · 2020-04-30T19:17:56Z

@ilya-epifanov what do you mean? Just to note: I'm not a maintainer of this repo and I don't even have a push access to your PR-branch.

ilya-epifanov · 2020-04-30T19:55:07Z

@Disasm I mean if this PR gets an approval from the most active reviewer, the maintainers will have a better idea of what's going on here 😀

Disasm · 2020-04-30T20:48:07Z

Well, if there are no objections, I think this PR is ready to get merged!

ilya-epifanov · 2020-04-30T20:52:01Z

@skade could you please take a look?

japaric · 2020-05-05T16:36:26Z

@ilya-epifanov thanks for the PR. For the time being, we (Ferrous) do not intend to continue working on this repository. Instead, we'd like the embedded community to continue to explore async/await on different embedded platforms and try out different things. For more details, check out our latest blog post.

Of course, you are more than welcome to continue working on a fork of this repo! You have made quite remarkable progress to make this work on RISCV so please keep going.

Disasm · 2020-05-05T17:32:47Z

@japaric That's unfortunate. Could we move this repo to the rust-embedded-community org?

jamesmunns · 2020-05-06T15:37:48Z

We've created https://github.com/rust-embedded-community/async-on-embedded/, could you please resubmit your PR there? Thank you!

ilya-epifanov commented Apr 3, 2020

View reviewed changes

ilya-epifanov added 2 commits April 27, 2020 23:54

abstracted async-cortex-m over specifics of WFE/SEV across ISAs. …

116a79d

…Added several RISC-V implementations of `WFE/SEV`, as RISC-V leaves implementation of these to SoC designers.

renamed async-cortex-m to async-embedded as it's now generic over…

f539683

… Cortex-M and RISC-V ISA's

Disasm reviewed Apr 28, 2020

View reviewed changes

removed isa-... features in favour of target_arch

30762d2

Disasm reviewed Apr 28, 2020

View reviewed changes

added target_arch = "riscv64"

26c3058

Disasm reviewed Apr 29, 2020

View reviewed changes

async-embedded/Cargo.toml Outdated Show resolved Hide resolved

s/wait-extern/riscv-wait-extern/

73edbac

Co-Authored-By: Vadim Kaushan <[email protected]>

jamesmunns closed this May 6, 2020

ilya-epifanov mentioned this pull request May 6, 2020

RISC-V support rust-embedded-community/async-on-embedded#4

Merged

	[target.'cfg(target_arch = "riscv32")'.dependencies]
	[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]

RISC-V support #3

RISC-V support #3

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ilya-epifanov commented Apr 30, 2020

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ilya-epifanov commented Apr 1, 2020 •

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ilya-epifanov commented Apr 27, 2020 •

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