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[SYCL][L0] Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2 #9109

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Merged
merged 2 commits into from
Apr 20, 2023
Merged

[SYCL][L0] Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2 #9109

merged 2 commits into from
Apr 20, 2023

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smaslov-intel
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@smaslov-intel smaslov-intel requested review from a team as code owners April 18, 2023 18:29
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@intel/llvm-gatekeepers : any idea what this means?

[2023-04-18T18:34:49.451Z] + python3 ./llvm_ci/jenkins/donb_dispatch_files/check_node.py -l ProtexIP_193_1681842364
[2023-04-18T18:34:51.411Z] /rdrive/ics/itools/pkgtools/python/v3_7_4/efi2_rhel511/lib/python3.7/site-packages/urllib3/connectionpool.py:1004: InsecureRequestWarning: Unverified HTTPS request is being made. Adding certificate verification is strongly advised. See: https://urllib3.readthedocs.io/en/latest/advanced-usage.html#ssl-warnings

@smaslov-intel smaslov-intel temporarily deployed to aws April 18, 2023 20:50 — with GitHub Actions Inactive
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@smaslov-intel smaslov-intel requested a review from a team as a code owner April 20, 2023 02:30
@smaslov-intel smaslov-intel requested a review from bso-intel April 20, 2023 02:30
@smaslov-intel smaslov-intel temporarily deployed to aws April 20, 2023 03:14 — with GitHub Actions Inactive
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AlexeySachkov
AlexeySachkov approved these changes Apr 20, 2023
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doc part LGTM

@againull againull merged commit 8543566 into intel:sycl Apr 20, 2023
jandres742 pushed a commit to jandres742/llvm that referenced this pull request Apr 21, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
c2415cb 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request Apr 24, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
6597294 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 3, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
da2691a 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
@smaslov-intel smaslov-intel deleted the resident branch May 12, 2023 19:13
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 16, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
f147249 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 23, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
9870c41 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 26, 2023
Port Change the default to SYCL_PI_LEVEL_ZERO_USM_RESIDENT=2
eb9b4b7 
intel#9109

Signed-off-by: Jaime Arteaga <[email protected]>
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@AlexeySachkov AlexeySachkov AlexeySachkov approved these changes

@againull againull againull approved these changes

@bso-intel bso-intel Awaiting requested review from bso-intel bso-intel is a code owner automatically assigned from intel/llvm-reviewers-runtime

+1 more reviewer

@jandres742 jandres742 jandres742 approved these changes

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4 participants
@smaslov-intel @AlexeySachkov @jandres742 @againull