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merged 2 commits into from
Jan 31, 2022
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Register definition refactoring #6

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bb2869d
[Z80] Register definition refactoring
b-s-a Dec 2, 2019
3a0d333
Cleanup #6.
jacobly0 Jan 31, 2022
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84 changes: 49 additions & 35 deletions llvm/lib/Target/Z80/Z80RegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -13,20 +13,41 @@
//
//===----------------------------------------------------------------------===//

class Z80Reg<string n, bits<16> Enc = -1> : Register<n> {
let Namespace = "Z80";
let HWEncoding = Enc;
}
class Z80RegWithSubRegs<string n, list<Register> sub = [], bits<16> enc = -1>
: Z80Reg<n, enc> {
let SubRegs = sub;
}

// Subregister indices.
let Namespace = "Z80" in {
class Z80Reg<string name, bits<16> enc = -1> : Register<name> {
let HWEncoding = enc;
}

// Subregister indices.
def sub_low : SubRegIndex<8>;
def sub_high : SubRegIndex<8, 8>;
def sub_short : SubRegIndex<16>;

class Z80RegPair<Z80Reg high, Z80Reg low,
bits<16> enc, bits<16> dwarf = enc>
: Z80Reg<!cond(!and(!eq(!size(high.AsmName), 1),
!eq(!size( low.AsmName), 1))
: !strconcat(high.AsmName, low.AsmName),
!and(!gt(!size(high.AsmName), 1),
!gt(!size( low.AsmName), 1),
!eq(!substr(high.AsmName,
0, !sub(!size(high.AsmName), 1)),
!substr( low.AsmName,
0, !sub(!size( low.AsmName), 1))))
: !substr(high.AsmName, 0, !sub(!size(high.AsmName), 1))),
enc>
, DwarfRegNum<[dwarf]> {
let SubRegs = [high, low];
let SubRegIndices = [sub_high, sub_low];
let CoveredBySubRegs = 1;
}

class EZ80ExtReg<Z80Reg short>
: Z80Reg<short.AsmName, short.HWEncoding>
, DwarfRegAlias<short> {
let SubRegs = [short];
let SubRegIndices = [sub_short];
}
}

//===----------------------------------------------------------------------===//
Expand All @@ -51,32 +72,35 @@ def IYH : Z80Reg<"iyh", 4>;
def IYL : Z80Reg<"iyl", 5>;
}

let SubRegIndices = [sub_high, sub_low], CoveredBySubRegs = 1 in {
// 16-bit registers
def AF : Z80RegWithSubRegs<"af", [A,F], 3>, DwarfRegNum<[3]>;
def BC : Z80RegWithSubRegs<"bc", [B,C], 0>, DwarfRegNum<[0]>;
def DE : Z80RegWithSubRegs<"de", [D,E], 1>, DwarfRegNum<[1]>;
def HL : Z80RegWithSubRegs<"hl", [H,L], 2>, DwarfRegNum<[2]>;
def AF : Z80RegPair<A, F, 3>;
def BC : Z80RegPair<B, C, 0>;
def DE : Z80RegPair<D, E, 1>;
def HL : Z80RegPair<H, L, 2>;

// 16-bit index registers
let CostPerUse = [1] in {
def IX : Z80RegWithSubRegs<"ix", [IXH,IXL], 2>, DwarfRegNum<[4]>;
def IY : Z80RegWithSubRegs<"iy", [IYH,IYL], 2>, DwarfRegNum<[5]>;
}
def IX : Z80RegPair<IXH, IXL, 2, 4>;
def IY : Z80RegPair<IYH, IYL, 2, 5>;
}

// 16-bit misc registers
def SPS : Z80Reg<"sp", 3>, DwarfRegNum<[6]>;

let SubRegIndices = [sub_short] in {
// 24-bit registers
def UBC : Z80RegWithSubRegs<"bc", [BC], 0>, DwarfRegAlias<BC>;
def UDE : Z80RegWithSubRegs<"de", [DE], 1>, DwarfRegAlias<DE>;
def UHL : Z80RegWithSubRegs<"hl", [HL], 2>, DwarfRegAlias<HL>;
def UBC : EZ80ExtReg<BC>;
def UDE : EZ80ExtReg<DE>;
def UHL : EZ80ExtReg<HL>;
// 24-bit index registers
let CostPerUse = [1] in {
def UIX : Z80RegWithSubRegs<"ix", [IX], 2>, DwarfRegAlias<IX>;
def UIY : Z80RegWithSubRegs<"iy", [IY], 2>, DwarfRegAlias<IY>;
}
def UIX : EZ80ExtReg<IX>;
def UIY : EZ80ExtReg<IY>;
}

// 24-bit misc registers
def SPL : Z80Reg<"sp", 3>, DwarfRegNum<[7]>;

// misc registers
def PC : Z80Reg<"pc">, DwarfRegNum<[8]>;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -105,11 +129,6 @@ def A16 : Z80RC16<(add HL, I16)>;
def R16 : Z80RC16<(add G16, I16)>;
let CopyCost = -1 in
def Z16 : Z80RC16<(add SPS, AF)>;
//def S16 : Z80RC16<(add R16, AF)>;
//def L16 : Z80RC16<(add G16, I16)>;
//def R16 : Z80RC16<(add L16, SPS)>;
//def S16 : Z80RC16<(add L16, AF)>;
//def C16 : Z80RC16<(add R16, SPS)>;

def O24 : Z80RC24<(add UDE, UBC)>;
def G24 : Z80RC24<(add UHL, O24)>;
Expand All @@ -120,8 +139,3 @@ def A24 : Z80RC24<(add UHL, I24)>;
def R24 : Z80RC24<(add G24, I24)>;
let CopyCost = -1 in
def Z24 : Z80RC24<(add SPL, PC)>;
//def S24 : Z80RC24<(add R24, AF)>;
//def L24 : Z80RC24<(add G24, I24)>;
//def R24 : Z80RC24<(add L24, SPL)>;
//def S24 : Z80RC24<(add L24, AF)>;
//def C24 : Z80RC24<(add R24, SPL)>;