Input impedance control of the clock terminal PFI4 on NI 6535

[zhang-wenjun]

Hi, I'm using PrawnBlaster to generate pseudoclock for my NI 6535 board. The clock terminal is set to PFI4 by

NI_PCIe_6535(
            name='ni_6535', parent_device=master_clock.clocklines[0],
            MAX_name='PCIe-6535-Dev1',
            clock_terminal='/PCIe-6535-Dev1/PFI4', # use PFI4 to receive clock from the master clock
            clock_mirror_terminal='/PCIe-6535-Dev1/PFI5', # use PFI5 to mirror clock from the master clock
            stop_order = -1) # 1st device in daisy chain, ensure it transitions to manual mode first

The NI_PCIe_6535 class is generated by labscript_devices/NI_DAQmx/models/generate_subclasses.py. The program compiled without any error. But I find that the high level voltage received by PFI4 is only ~1.3V when running digital output tasks, which means the input impedance of PFI4 port is only ~50Ohm, instead of 50kOhm, given the output driving ability of rp2040 GPIO.

When I use LabVIEW to do digital output, the input impedance is correct (a high value, I did not measure the exact number) and the high level is indeed 3.3V, so I think the NI board is fine.

I see the underlying worker uses DAQmxCfgSampClkTiming to configure this function. So I'm wondering if there are any other steps (like config. in NI-MAX, or config. in generate_subclasses.py, etc.) to correctly configure the input impedance.

Thanks!

[chrisjbillington]

Hi Zhang-Wenjun,

Here's some discussion of this that has previously appeared on the mailing list:

https://groups.google.com/g/labscriptsuite/c/jsbbgoZqJtU

The issue seems to have something to do with the fact that the PFI terminal is initially configured as an output when BLACS is in manual mode. Firstly, did you measure the impedance during a buffered run, or only when BLACS was in manual mode? If the latter, it is possible that the terminal does have high impedance during a buffered run.

If not, and if you aren't otherwise using the other terminals on the port as static digital outputs, you might consider disabling the whole port. This would make the configuration in labscript closer to what LabVIEW is likely doing in your testing.

To disable the port, you can pass in a custom ports keyword argument that excludes the entire port of digital outputs that includes the terminal in question.

Here's the CAPABILITIES dict for that model:

CAPABILITIES = {
    'AI_range': None,
    'AI_range_Diff': None,
    'AI_start_delay': None,
    'AO_range': None,
    'max_AI_multi_chan_rate': None,
    'max_AI_single_chan_rate': None,
    'max_AO_sample_rate': None,
    'max_DO_sample_rate': 10000000.0,
    'min_semiperiod_measurement': None,
    'num_AI': 0,
    'num_AO': 0,
    'num_CI': 0,
    'ports': {
        'port0': {'num_lines': 8, 'supports_buffered': True},
        'port1': {'num_lines': 8, 'supports_buffered': True},
        'port2': {'num_lines': 8, 'supports_buffered': True},
        'port3': {'num_lines': 8, 'supports_buffered': True},
        'port4': {'num_lines': 6, 'supports_buffered': False},
    },
    'supports_buffered_AO': False,
    'supports_buffered_DO': True,
    'supports_semiperiod_measurement': False,
}

which lists 5 ports.

So you could for example do something like the following to configure the device to ignore port4 for the purpose of digital output:

from blahblah import NI_PCIe_6535, CAPABILTIES

custom_ports_config = CAPABILTIES['ports'].copy()
del custom_ports_config['port4']


NI_PCIe_6535(
            name='ni_6535', parent_device=master_clock.clocklines[0],
            MAX_name='PCIe-6535-Dev1',
            clock_terminal='/PCIe-6535-Dev1/PFI4', # use PFI4 to receive clock from the master clock
            clock_mirror_terminal='/PCIe-6535-Dev1/PFI5', # use PFI5 to mirror clock from the master clock
            stop_order = -1, # 1st device in daisy chain, ensure it transitions to manual mode first
            ports=custom_ports_config)

[zhang-wenjun]

Thanks a lot Chris! This solved my issue. Indeed, I was testing in the manual mode. I just retry and measure in the buffered mode and it seems normal. The custom_ports method is also very useful to me. BTW, adding a driving buffer for RPiPico that can drive 50Ohm load can potentially put the NI board at risk. It will produce ~66mA current on the PFI port. I previously consulted an NI engineer and was not recommended to do so.

Thanks again!