Added POLARBERRY board support (SundanceDSP company)

Config.in

@@ -11,6 +11,7 @@ source "$BR2_EXTERNAL_MCHP_PATH/package/wilcmchp_firmware/Config.in"
 source "$BR2_EXTERNAL_MCHP_PATH/package/9bit/Config.in"
 source "$BR2_EXTERNAL_MCHP_PATH/package/plplot/Config.in"
 source "$BR2_EXTERNAL_MCHP_PATH/package/mpfs_examples/Config.in"
+source "$BR2_EXTERNAL_MCHP_PATH/package/hart-software-services/Config.in"
 source "$BR2_EXTERNAL_MCHP_PATH/package/hss-payload-generator/Config.in.host"
 source "$BR2_EXTERNAL_MCHP_PATH/package/mpfs_amp_examples/Config.in"
 

board/microchip/polarberry/FLASH_CONFIG.CONF

@@ -0,0 +1,5 @@
+BUILDROOT_DIRECTORY="/home/sundancedsp_polarberry/buildroot-2023.08.1"	#set here path the buildroot you are used for building
+UART_DEVICE="/dev/ttyUSB0"							#set here POLARBERRY board UART device in linux
+DEVICE_IP="192.168.1.72"							#set here IP ADDRESS used for POLARBERRY board that you want to flash 
+PC_IP="192.168.1.177"								#set here IP ADDRESS of you PC
+IMAGE_NAME="fitimage_polarberry.itb"						#set here file name of the linux image (it shall be placed in the TFTP directory)

board/microchip/polarberry/README

@@ -0,0 +1,100 @@
+
+There are 4 scipts:
+1) Program_HSS_to_eNVM.sh
+2) Program_UBOOT_to_eMMC.sh
+3) Program_LINUX_to_eNVM.sh
+4) Program_ALL_to_Polarberry.sh
+
+and settings file: FLASH_CONFIG.CONF
+
+Script is used to burn images to the Polarberry board.
+
+The 1th is used to program ONLY HSS bootloader umage to the Polarberry board.
+The 2th is used to program ONLY UBOOT image to the Polarberry board.
+The 3th is used to program ONLY LINUX (Kernel and root filesystem, bith) image to the Polarberry board.
+The 4th is used to program ALL (HSS, UBOOT, LINUX) images to the Polarberry oard.
+
+
+The 1th script can be used with virgin Polarberry boards and requires ONLY JTAG connection with the board.
+The 2th script can be used only after 1th was used (it means UBOOT programming requires HSS was installed before) 
+    and requires JTAG and UART connection with the board.
+The 3th script can be used only after 2th was used (it means Linux programming requires UBOOT (as HSS toot)
+    was installed before) and requires JTAG, UART and ETHERNET connection with the board.
+The 4th script runs 1,2,3 one-by-one and do all thunigs that do 1,2,3 in automatic mode and requires JTAG
+    UART and ETHERNET connection with the board. Can be used with virgin Polarberry boards too.
+
+Before script can be used, you need to fix values in FLASH_CONFIG.CONF according to your PC.
+The file contains strings with comments, so you can advice what you need:
+
+BUILDROOT_DIRECTORY	- here you need to set PATH to the buildroot you are using
+UART_DEVICE		- here you need to set the name of the UART in your system. (/dev/ttyUSB1 for example)
+DEVICE_IP		- here you need to set IP ADDRESS that will be set on the board during flashing.
+                          It shall be one of the free/unused IP addresses from you network.
+
+PC_IP			- here you need to set IP ADDRESS of the PC you are using. (It can be obtained via "ifconfig" command)
+IMAGE_NAME		- here you need to set file name with LINUX image that is placed on the TFTP server
+                          (default value is "fitimage_polarberry.itb", and this file is built by buildroot and placed in "output/images" directory)
+
+
+To start building images via buildroot you need to run this command in buildrood sources:
+1) "make sundancedsp_polarberry_defconfig  BR2_EXTERNAL=../buildroot-external-microchip"
+   (where BR2_EXTERNAL shall point to the mbuildroot microsemi sources).
+
+2) "make"
+    Building will take time. Succesfull building will finish like this:
+
+FIT description: Linux fitImage for Polaberry
+Created:         Wed Nov 22 05:06:16 2023
+ Image 0 (kernel-0)
+  Description:  Linux Kernel
+  Created:      Wed Nov 22 05:06:16 2023
+  Type:         Kernel Image
+  Compression:  uncompressed
+  Data Size:    17612800 Bytes = 17200.00 KiB = 16.80 MiB
+  Architecture: RISC-V
+  OS:           Linux
+  Load Address: 0x80200000
+  Entry Point:  0x80200000
+  Hash algo:    sha256
+  Hash value:   466f36e4c778103ce7ef2fa9dc3456cb1e25d291fe71ab96f3d88ac588004f11
+ Image 1 (fdt-0)
+  Description:  Flattened Device Tree blob
+  Created:      Wed Nov 22 05:06:16 2023
+  Type:         Flat Device Tree
+  Compression:  uncompressed
+  Data Size:    14949 Bytes = 14.60 KiB = 0.01 MiB
+  Architecture: RISC-V
+  Hash algo:    sha256
+  Hash value:   1ccea6c67588f89a9227a5018b98048390728ef3a21ba90cbd69d8ab750843a4
+ Image 2 (ramdisk-0)
+  Description:  ramdisk
+  Created:      Wed Nov 22 05:06:16 2023
+  Type:         RAMDisk Image
+  Compression:  uncompressed
+  Data Size:    4921601 Bytes = 4806.25 KiB = 4.69 MiB
+  Architecture: AArch64
+  OS:           Linux
+  Load Address: unavailable
+  Entry Point:  unavailable
+  Hash algo:    sha256
+  Hash value:   cae144f8a5c8eb441ba01aae3d3dc1c88ea0303afe710e7d7528d04b0e963997
+ Default Configuration: 'conf-1'
+ Configuration 0 (conf-1)
+  Description:  Boot Linux kernel with FDT blob + ramdisk
+  Kernel:       kernel-0
+  Init Ramdisk: ramdisk-0
+  FDT:          fdt-0
+  Hash algo:    sha256
+  Hash value:   unavailable
+ Configuration 1 (conf-2)
+  Description:  Boot Linux kernel with FDT blob
+  Kernel:       kernel-0
+  FDT:          fdt-0
+  Hash algo:    sha256
+  Hash value:   unavailable
+
+
+To flash the images to the Polarberry board:
+1) Fix FLASH_CONFIG.CONF file in the board/microchip/polarberry directory.
+2) Power ON the Polarberry board
+3) run "Program_ALL_to_Polarberry.sh", and wait until all finished.

board/microchip/polarberry/fitimage_polarberry.its

@@ -0,0 +1,66 @@
+/dts-v1/;
+
+/ {
+	description = "Linux fitImage for Polaberry";
+	#address-cells = <1>;
+
+	images {
+		kernel-0 {
+			description = "Linux Kernel";
+			data = /incbin/("images/Image");
+			type = "kernel";
+			arch = "riscv";
+			os = "linux";
+			compression = "none";
+			load = <0x80200000>;
+			entry = <0x80200000>;
+			hash-1 {
+				algo = "sha256";
+			};
+		};
+
+		fdt-0 {
+			description = "Flattened Device Tree blob";
+			data = /incbin/("images/linux_polarberry.dtb");
+			type = "flat_dt";
+			arch = "riscv";
+			compression = "none";
+			hash-1 {
+				algo = "sha256";
+			};
+		};
+
+		ramdisk-0 {
+			description = "ramdisk";
+			data = /incbin/("images/rootfs.cpio.bz2");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "none";
+			hash-1 {
+				algo = "sha256";
+			};
+		};
+	};
+
+	configurations {
+		default = "conf-1";
+		conf-1 {
+			description = "Boot Linux kernel with FDT blob + ramdisk";
+			kernel = "kernel-0";
+			fdt = "fdt-0";
+			ramdisk = "ramdisk-0";
+			hash-1 {
+				algo = "sha256";
+			};
+		};
+		conf-2 {
+			description = "Boot Linux kernel with FDT blob";
+			kernel = "kernel-0";
+			fdt = "fdt-0";
+			hash-1 {
+				algo = "sha256";
+			};
+		};
+	};
+};

board/microchip/polarberry/linux/linux_polarberry.dts

@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "microchip/mpfs.dtsi"
+#include "microchip/mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ	1000000
+
+/ {
+	model = "Microchip POLARBERRY";
+	compatible = "microchip,mpfs";
+
+	aliases {
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+//		spi0 = &spi0;
+//		qspi = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <MTIMER_FREQ>;
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x2e000000>;
+	};
+
+	ddrc_cache_hi: memory@1000000000 {
+		device_type = "memory";
+		reg = <0x10 0x00000000 0x0 0xC0000000>;
+	};
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy4>;
+	status = "disabled";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy5>;
+	status = "okay";
+
+	phy4: ethernet-phy@4 { // This PHY is connected to mac0, but the port itself is on the (optional) carrier board.
+		reg = <4>;
+	};
+
+	phy5: ethernet-phy@5 { // This PHY is connected to mac1, but the port itself is on the SOM (PolarBerry) board.
+		reg = <5>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&i2c0 {
+	// 0x72 = SI538A-B-GM
+
+    status = "okay";
+};
+
+&i2c1 {
+    status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "n25q00a";
+		reg = <0x0>;
+
+		spi-max-frequency = <10000000>;
+
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+
+		partition@0 {
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x2000000>; //32Mb
+		};
+
+		partition@2000000 {
+			label = "qspi-linux";
+			reg = <0x2000000 0x6000000>; //96Mb
+		};
+	};
+};
+
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&mmuart0 {
+	status = "okay";
+};
+
+&mmuart1 {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};