Skip to content

[SV] Enhanced name validation: support IEEE standard escape name checking #8518

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: main
Choose a base branch
from

Conversation

RonxBulld
Copy link

Change Overview

This PR updates the name validation mechanism in the SV dialect, mainly modifying the isNameValid function in the SVDialect.h and LegalizeNames.cpp files to support escaped name checking in accordance with the IEEE standard.

Change Reason

  1. IEEE Standard Compliance: The original name validation function lacks the correct handling of escaped identifiers in the IEEE Verilog standard. The IEEE 1800 standard allows backslash-escaped identifiers (such as \escaped_name), which are common in Verilog code generation.

  2. Function Enhancement: By adding a new allowEscapedName parameter, the isNameValid function can decide whether to allow escaped names based on the context, providing a more flexible name validation strategy.

  3. Backward compatibility: The modification maintains compatibility with existing APIs while expanding functionality so that callers can choose whether to enable escape name support as needed.

  4. Code generation quality: Correct handling of escape names can avoid illegal identifiers during Verilog code generation, improving the quality and standard compliance of generated code.

Major changes

  • Modify isNameValid function signature and add allowEscapedName parameter
  • Update related call sites to pass new parameters
  • Enhance name validation logic to support IEEE standard escape identifier format

…function to support IEEE compliant escaped name checking. Adjusted related calls to enable new parameter allowEscapedName.
@RonxBulld RonxBulld requested a review from darthscsi as a code owner May 29, 2025 14:24
Copy link
Member

@seldridge seldridge left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks for starting this. I've actually wanted to use this in a couple places and thought it would require way more effort to get working.

Can you include at least one test of this behavior? E.g., this might be a good place: https://github.com/llvm/circt/blob/main/test/Conversion/ExportVerilog/name-legalize.mlir

Comment on lines 48 to 51
/// If \p allowEscapedName is true, IEEE-compliant escaped names are allowed to
/// pass the check.
bool isNameValid(llvm::StringRef name, bool caseInsensitiveKeywords,
bool allowEscapedName = false);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Escaped names are legal in both Verilog (1364-1995 2.7.1) and SystemVerilog (1800-2023 5.6.1). I don't see a good reason to make this optionally allowed given that (I think) all Verilog versions support escaped identifiers. The only difference is on what the identifiers are.

Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Escaped names are legal in both Verilog (1364-1995 2.7.1) and SystemVerilog (1800-2023 5.6.1). I don't see a good reason to make this optionally allowed given that (I think) all Verilog versions support escaped identifiers. The only difference is on what the identifiers are.

Yes, I concur with your viewpoint and believe that this feature should be enabled by default. Given that my understanding of CIRCT is not particularly in-depth, I am not entirely certain whether this modification might cause any side effects. Out of caution, I have temporarily set it as an optional feature, hoping that it will at least meet my needs. After extensive validation, you, I, or anyone else can set it as a default feature, which I consider to be a prudent choice.

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

+1, I think default is better.

@RonxBulld
Copy link
Author

Thanks for starting this. I've actually wanted to use this in a couple places and thought it would require way more effort to get working.

Can you include at least one test of this behavior? E.g., this might be a good place: https://github.com/llvm/circt/blob/main/test/Conversion/ExportVerilog/name-legalize.mlir

Thank you for your reminder. I will add some tests at a later time.

RonxBulld added 2 commits May 31, 2025 01:16
… new module instances, moduleInstEscNameModExt and moduleInstEscNameModExt2, to ensure they handle escape characters correctly. This change enhances support for IEEE-compliant escaped names.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants