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[CIR][CIRGen][Builtin][Neon] Lower vrnd32z and vrnd32zq #1399

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Merged
merged 1 commit into from
Feb 24, 2025
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[CIR][CIRGen][Builtin][Neon] Lower vrnd32z and vrnd32zq #1399

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14 changes: 8 additions & 6 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2627,6 +2627,14 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
argTypes.push_back(vTy);
break;
}
case NEON::BI__builtin_neon_vrnd32z_f32:
case NEON::BI__builtin_neon_vrnd32zq_f32:
case NEON::BI__builtin_neon_vrnd32z_f64:
case NEON::BI__builtin_neon_vrnd32zq_f64: {
intrincsName = "aarch64.neon.frint32z";
argTypes.push_back(vTy);
break;
}
case NEON::BI__builtin_neon_vshl_v:
case NEON::BI__builtin_neon_vshlq_v: {
return builder.create<cir::ShiftOp>(
Expand Down Expand Up @@ -4194,12 +4202,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vrndh_f16: {
llvm_unreachable("NEON::BI__builtin_neon_vrndh_f16 NYI");
}
case NEON::BI__builtin_neon_vrnd32z_f32:
case NEON::BI__builtin_neon_vrnd32zq_f32:
case NEON::BI__builtin_neon_vrnd32z_f64:
case NEON::BI__builtin_neon_vrnd32zq_f64: {
llvm_unreachable("NEON::BI__builtin_neon_vrnd32zq_f64 NYI");
}
case NEON::BI__builtin_neon_vrnd64x_f32:
case NEON::BI__builtin_neon_vrnd64xq_f32:
case NEON::BI__builtin_neon_vrnd64x_f64:
Expand Down
64 changes: 40 additions & 24 deletions clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
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Original file line number Diff line number Diff line change
Expand Up @@ -42,19 +42,27 @@ float32x4_t test_vrnd32xq_f32(float32x4_t a) {
// LLVM: ret <4 x float> [[RND]]
}

// CHECK-LABEL: test_vrnd32z_f32
// CHECK: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[RND]]
// float32x2_t test_vrnd32z_f32(float32x2_t a) {
// return vrnd32z_f32(a);
// }
float32x2_t test_vrnd32z_f32(float32x2_t a) {
return vrnd32z_f32(a);

// CHECK-LABEL: test_vrnd32zq_f32
// CHECK: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[RND]]
// float32x4_t test_vrnd32zq_f32(float32x4_t a) {
// return vrnd32zq_f32(a);
// }
// CIR-LABEL: vrnd32z_f32
// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32z" {{.*}} : (!cir.vector<!cir.float x 2>) -> !cir.vector<!cir.float x 2>

// LLVM-LABEL: @test_vrnd32z_f32
// LLVM: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %0)
// LLVM: ret <2 x float> [[RND]]
}

float32x4_t test_vrnd32zq_f32(float32x4_t a) {
return vrnd32zq_f32(a);

// CIR-LABEL: vrnd32zq_f32
// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32z" {{.*}} : (!cir.vector<!cir.float x 4>) -> !cir.vector<!cir.float x 4>

// LLVM-LABEL: @test_vrnd32zq_f32
// LLVM: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %0)
// LLVM: ret <4 x float> [[RND]]
}

// CHECK-LABEL: test_vrnd64x_f32
// CHECK: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %a)
Expand Down Expand Up @@ -107,19 +115,27 @@ float64x2_t test_vrnd32xq_f64(float64x2_t a) {
// LLVM: ret <2 x double> [[RND]]
}

// CHECK-LABEL: test_vrnd32z_f64
// CHECK: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32z.v1f64(<1 x double> %a)
// CHECK: ret <1 x double> [[RND]]
// float64x1_t test_vrnd32z_f64(float64x1_t a) {
// return vrnd32z_f64(a);
// }
float64x1_t test_vrnd32z_f64(float64x1_t a) {
return vrnd32z_f64(a);

// CHECK-LABEL: test_vrnd32zq_f64
// CHECK: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32z.v2f64(<2 x double> %a)
// CHECK: ret <2 x double> [[RND]]
// float64x2_t test_vrnd32zq_f64(float64x2_t a) {
// return vrnd32zq_f64(a);
// }
// CIR-LABEL: vrnd32z_f64
// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32z" {{.*}} : (!cir.vector<!cir.double x 1>) -> !cir.vector<!cir.double x 1>

// LLVM-LABEL: @test_vrnd32z_f64
// LLVM: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32z.v1f64(<1 x double> %0)
// LLVM: ret <1 x double> [[RND]]
}

float64x2_t test_vrnd32zq_f64(float64x2_t a) {
return vrnd32zq_f64(a);

// CIR-LABEL: vrnd32zq_f64
// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32z" {{.*}} : (!cir.vector<!cir.double x 2>) -> !cir.vector<!cir.double x 2>

// LLVM-LABEL: @test_vrnd32zq_f64
// LLVM: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32z.v2f64(<2 x double> %0)
// LLVM: ret <2 x double> [[RND]]
}

// CHECK-LABEL: test_vrnd64x_f64
// CHECK: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64x.v1f64(<1 x double> %a)
Expand Down
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