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[CIR] Improved cir::CastOp verifier to allow bitcasts between types of the same size #1728

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12 changes: 12 additions & 0 deletions clang/lib/CIR/Dialect/IR/CIRDialect.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@
#include "mlir/IR/Location.h"
#include "mlir/IR/OpDefinition.h"
#include "mlir/IR/OpImplementation.h"
#include "mlir/IR/Operation.h"
#include "mlir/IR/StorageUniquerSupport.h"
#include "mlir/IR/TypeUtilities.h"
#include "mlir/Interfaces/DataLayoutInterfaces.h"
Expand Down Expand Up @@ -570,6 +571,17 @@ LogicalResult cir::CastOp::verify() {
mlir::isa<cir::MethodType>(resType))
return success();

// Handle scalar to vector and vector to scalar conversions.
if (mlir::isa<cir::VectorType>(getSrc().getType()) !=
mlir::isa<cir::VectorType>(getType())) {
// The source and result must be the same size.
mlir::DataLayout dataLayout(
getOperation()->getParentOfType<mlir::DataLayoutOpInterface>());
if (dataLayout.getTypeSize(getSrc().getType()) ==
dataLayout.getTypeSize(getType()))
return success();
}

// This is the only cast kind where we don't want vector types to decay
// into the element type.
if ((!mlir::isa<cir::VectorType>(getSrc().getType()) ||
Expand Down
22 changes: 17 additions & 5 deletions clang/test/CIR/CodeGen/vectype.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -120,19 +120,31 @@ void vector_int_test(int x, unsigned short usx) {

// Shifts
vi4 w = a << b;
// CHECK: %{{[0-9]+}} = cir.shift(left, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK: %{{[0-9]+}} = cir.shift(left, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK-SAME: {{%.*}} : !cir.vector<!s32i x 4>) -> !cir.vector<!s32i x 4>
vi4 y = a >> b;
// CHECK: %{{[0-9]+}} = cir.shift(right, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK: %{{[0-9]+}} = cir.shift(right, {{%.*}} : !cir.vector<!s32i x 4>,
// CHECK-SAME: {{%.*}} : !cir.vector<!s32i x 4>) -> !cir.vector<!s32i x 4>

vus2 z = { usx, usx };
vus2 z = { usx, usx };
// CHECK: %{{[0-9]+}} = cir.vec.create(%{{[0-9]+}}, %{{[0-9]+}} : !u16i, !u16i) : !cir.vector<!u16i x 2>
vus2 zamt = { 3, 4 };
// CHECK: %{{[0-9]+}} = cir.const #cir.const_vector<[#cir.int<3> : !u16i, #cir.int<4> : !u16i]> : !cir.vector<!u16i x 2>
vus2 zzz = z >> zamt;
// CHECK: %{{[0-9]+}} = cir.shift(right, {{%.*}} : !cir.vector<!u16i x 2>,
// CHECK-SAME: {{%.*}} : !cir.vector<!u16i x 2>) -> !cir.vector<!u16i x 2>
// CHECK: %{{[0-9]+}} = cir.shift(right, {{%.*}} : !cir.vector<!u16i x 2>,
// CHECK-SAME: {{%.*}} : !cir.vector<!u16i x 2>) -> !cir.vector<!u16i x 2>

// Vector to scalar conversion
unsigned int zi = (unsigned int)z;
// CHECK: %{{[0-9]+}} = cir.cast(bitcast, {{%.*}} : !cir.vector<!u16i x 2>), !u32i

// Scalar to vector conversion
vus2 zz = (vus2)zi;
// CHECK: %{{[0-9]+}} = cir.cast(bitcast, {{%.*}} : !u32i), !cir.vector<!u16i x 2>

// Vector to vector conversion
vll2 aaa = (vll2)a;
// CHECK: %{{[0-9]+}} = cir.cast(bitcast, {{%.*}} : !cir.vector<!s32i x 4>), !cir.vector<!s64i x 2>
}

void vector_double_test(int x, double y) {
Expand Down
28 changes: 28 additions & 0 deletions clang/test/CIR/IR/invalid.cir
Original file line number Diff line number Diff line change
Expand Up @@ -1405,7 +1405,35 @@ module {
// expected-error@+1 {{'cir.cast' op result type address space does not match the address space of the operand}}
%1 = cir.cast(bitcast, %0 : !cir.ptr<!s32i>), !cir.ptr<!s32i, addrspace(offload_local)>
}
}

// -----

!s16i = !cir.int<s, 16>
!s64i = !cir.int<s, 64>

module {
cir.func @test_bitcast_vec2scalar_diff_size() {
%0 = cir.const #cir.int<1> : !s16i
%1 = cir.vec.create(%0, %0 : !s16i, !s16i) : !cir.vector<!s16i x 2>
// expected-error@+1 {{'cir.cast' op requires !cir.ptr or !cir.vector type for source and result}}
%2 = cir.cast(bitcast, %1 : !cir.vector<!s16i x 2>), !s64i
cir.return
}
}

// -----

!s32i = !cir.int<s, 32>
!s64i = !cir.int<s, 64>

module {
cir.func @test_bitcast_scalar2vec_diff_size() {
%0 = cir.const #cir.int<1> : !s64i
// expected-error@+1 {{'cir.cast' op requires !cir.ptr or !cir.vector type for source and result}}
%1 = cir.cast(bitcast, %0 : !s64i), !cir.vector<!s32i x 4>
cir.return
}
}

// -----
Expand Down
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