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Merged
merged 1 commit into from
May 30, 2023
Merged

PR for llvm/llvm-project#62839 #452

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15 changes: 14 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -499,7 +499,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}

if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
setOperationAction(ISD::PREFETCH , MVT::Other, Custom);

setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);

Expand Down Expand Up @@ -33093,6 +33093,18 @@ static SDValue LowerCVTPS2PH(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
}

static SDValue LowerPREFETCH(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();

// We don't support non-data prefetch without PREFETCHI.
// Just preserve the chain.
if (!IsData && !Subtarget.hasPREFETCHI())
return Op.getOperand(0);

return Op;
}

static StringRef getInstrStrFromOpNo(const SmallVectorImpl<StringRef> &AsmStrs,
unsigned OpNo) {
const APInt Operand(32, OpNo);
Expand Down Expand Up @@ -33294,6 +33306,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION(Op, DAG);
case ISD::ADDRSPACECAST: return LowerADDRSPACECAST(Op, DAG);
case X86ISD::CVTPS2PH: return LowerCVTPS2PH(Op, DAG);
case ISD::PREFETCH: return LowerPREFETCH(Op, Subtarget, DAG);
}
}

Expand Down
5 changes: 5 additions & 0 deletions llvm/test/CodeGen/X86/prefetchi.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchi | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=NOPREFETCHI

define dso_local void @t(ptr %ptr) nounwind {
; CHECK-LABEL: t:
Expand All @@ -9,6 +10,10 @@ define dso_local void @t(ptr %ptr) nounwind {
; CHECK-NEXT: prefetchit1 t(%rip)
; CHECK-NEXT: prefetchit0 ext(%rip)
; CHECK-NEXT: retq
;
; NOPREFETCHI-LABEL: t:
; NOPREFETCHI: # %bb.0: # %entry
; NOPREFETCHI-NEXT: retq
entry:
tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 2, i32 0)
tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)
Expand Down