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[AMDGPU][AsmParser][NFC] Generate printers for named-bit operands automatically.
Part of <#62629>. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D154433
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+4
-99
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3 files changed

+4
-99
lines changed

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 0 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -100,21 +100,6 @@ void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
100100
}
101101
}
102102

103-
void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
104-
raw_ostream &O) {
105-
printNamedBit(MI, OpNo, O, "offen");
106-
}
107-
108-
void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
109-
raw_ostream &O) {
110-
printNamedBit(MI, OpNo, O, "idxen");
111-
}
112-
113-
void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
114-
raw_ostream &O) {
115-
printNamedBit(MI, OpNo, O, "addr64");
116-
}
117-
118103
void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
119104
const MCSubtargetInfo &STI,
120105
raw_ostream &O) {
@@ -186,11 +171,6 @@ void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
186171
printU32ImmOperand(MI, OpNo, STI, O);
187172
}
188173

189-
void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
190-
const MCSubtargetInfo &STI, raw_ostream &O) {
191-
printNamedBit(MI, OpNo, O, "gds");
192-
}
193-
194174
void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
195175
const MCSubtargetInfo &STI, raw_ostream &O) {
196176
auto Imm = MI->getOperand(OpNo).getImm();
@@ -208,11 +188,6 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
208188
O << " /* unexpected cache policy bit */";
209189
}
210190

211-
void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
212-
const MCSubtargetInfo &STI, raw_ostream &O) {
213-
printNamedBit(MI, OpNo, O, "tfe");
214-
}
215-
216191
void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
217192
const MCSubtargetInfo &STI, raw_ostream &O) {
218193
if (MI->getOperand(OpNo).getImm()) {
@@ -233,16 +208,6 @@ void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
233208
O << Dim;
234209
}
235210

236-
void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
237-
const MCSubtargetInfo &STI, raw_ostream &O) {
238-
printNamedBit(MI, OpNo, O, "unorm");
239-
}
240-
241-
void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
242-
const MCSubtargetInfo &STI, raw_ostream &O) {
243-
printNamedBit(MI, OpNo, O, "da");
244-
}
245-
246211
void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
247212
const MCSubtargetInfo &STI, raw_ostream &O) {
248213
if (STI.hasFeature(AMDGPU::FeatureR128A16))
@@ -251,33 +216,6 @@ void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
251216
printNamedBit(MI, OpNo, O, "r128");
252217
}
253218

254-
void AMDGPUInstPrinter::printA16(const MCInst *MI, unsigned OpNo,
255-
const MCSubtargetInfo &STI, raw_ostream &O) {
256-
printNamedBit(MI, OpNo, O, "a16");
257-
}
258-
259-
void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
260-
const MCSubtargetInfo &STI, raw_ostream &O) {
261-
printNamedBit(MI, OpNo, O, "lwe");
262-
}
263-
264-
void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
265-
const MCSubtargetInfo &STI, raw_ostream &O) {
266-
printNamedBit(MI, OpNo, O, "d16");
267-
}
268-
269-
void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
270-
const MCSubtargetInfo &STI,
271-
raw_ostream &O) {
272-
printNamedBit(MI, OpNo, O, "compr");
273-
}
274-
275-
void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
276-
const MCSubtargetInfo &STI,
277-
raw_ostream &O) {
278-
printNamedBit(MI, OpNo, O, "vm");
279-
}
280-
281219
void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
282220
const MCSubtargetInfo &STI,
283221
raw_ostream &O) {
@@ -1324,18 +1262,6 @@ void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
13241262
O << Asm;
13251263
}
13261264

1327-
void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1328-
const MCSubtargetInfo &STI,
1329-
raw_ostream &O) {
1330-
printNamedBit(MI, OpNo, O, "high");
1331-
}
1332-
1333-
void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1334-
const MCSubtargetInfo &STI,
1335-
raw_ostream &O) {
1336-
printNamedBit(MI, OpNo, O, "clamp");
1337-
}
1338-
13391265
void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
13401266
const MCSubtargetInfo &STI,
13411267
raw_ostream &O) {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
4747
const MCSubtargetInfo &STI, raw_ostream &O);
4848
void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
4949
StringRef BitName);
50-
void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51-
void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52-
void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
5350
void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
5451
raw_ostream &O);
5552
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -67,32 +64,14 @@ class AMDGPUInstPrinter : public MCInstPrinter {
6764
const MCSubtargetInfo &STI, raw_ostream &O);
6865
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
6966
const MCSubtargetInfo &STI, raw_ostream &O);
70-
void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
71-
raw_ostream &O);
7267
void printCPol(const MCInst *MI, unsigned OpNo,
7368
const MCSubtargetInfo &STI, raw_ostream &O);
74-
void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
75-
raw_ostream &O);
7669
void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
7770
raw_ostream &O);
7871
void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
7972
raw_ostream &O);
80-
void printUNorm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
81-
raw_ostream &O);
82-
void printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
83-
raw_ostream &O);
8473
void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
8574
raw_ostream &O);
86-
void printA16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
87-
raw_ostream &O);
88-
void printLWE(const MCInst *MI, unsigned OpNo,
89-
const MCSubtargetInfo &STI, raw_ostream &O);
90-
void printD16(const MCInst *MI, unsigned OpNo,
91-
const MCSubtargetInfo &STI, raw_ostream &O);
92-
void printExpCompr(const MCInst *MI, unsigned OpNo,
93-
const MCSubtargetInfo &STI, raw_ostream &O);
94-
void printExpVM(const MCInst *MI, unsigned OpNo,
95-
const MCSubtargetInfo &STI, raw_ostream &O);
9675
void printFORMAT(const MCInst *MI, unsigned OpNo,
9776
const MCSubtargetInfo &STI, raw_ostream &O);
9877
void printSymbolicFormat(const MCInst *MI,
@@ -202,12 +181,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
202181
protected:
203182
void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
204183
raw_ostream &O);
205-
void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
206-
raw_ostream &O);
207184
void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
208185
raw_ostream &O);
209-
void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
210-
raw_ostream &O);
211186
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
212187
raw_ostream &O);
213188
void printLiteral(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1047,12 +1047,16 @@ class NamedBitOperand<string Id, string Name = NAME>
10471047
let ParserMethod =
10481048
"[this](OperandVector &Operands) -> ParseStatus { "#
10491049
"return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy#"); }";
1050+
let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "#
1051+
"const MCSubtargetInfo &STI, raw_ostream &O) { "#
1052+
"printNamedBit(MI, OpNo, O, \""#Id#"\"); }";
10501053
}
10511054

10521055
class DefaultOperand<CustomOperand Op, int Value>
10531056
: OperandWithDefaultOps<Op.Type, (ops (Op.Type Value))>,
10541057
CustomOperandProps<1, Op.ParserMatchClass.Name> {
10551058
let ParserMethod = Op.ParserMatchClass.ParserMethod;
1059+
let PrintMethod = Op.PrintMethod;
10561060
}
10571061

10581062
class SDWAOperand<string Id, string Name = NAME>

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